16.5.2 Channel n Generator Selection

Each channel can be connected to one event generator. Not all generators can be connected to all channels. Refer to the table below to see which generator sources can be routed onto each channel and the generator value to be written to EVSYS.CHANNELn to achieve this routing. Writing the value 0x00 to EVSYS.CHANNELn turns the channel off.

Refer to the Peripheral Overview section for the available number of Event System channels.

Name:	CHANNELn
Offset:	0x10 + n*0x01 [n=0..5]
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	CHANNELn[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – CHANNELn[7:0] Channel Generator Selection

The specific generator name corresponding to each bit group configuration is given by combining Peripheral and Output from the table below in the following way: PERIPHERAL_OUTPUT.


GENERATOR			Async/Sync	Description	Channel Availability
Value	Name
Value	Peripheral	Output
`0x01`	UPDI	SYNCH	Async	Rising edge of SYNCH character detection	All channels
`0x06`	RTC	OVF	Async	Counter overflow	All channels
`0x07`		CMP		Compare match	All channels
`0x08`		EVGEN0		Selectable prescaled RTC event	All channels
`0x09`		EVGEN1		Selectable prescaled RTC event	All channels
`0x10`	CCL	LUT0	Async	LUT output level	All channels
`0x11`		LUT1
`0x12`		LUT2
`0x13`		LUT3
`0x20`	AC0	OUT	Async	Comparator output level	All channels
`0x21`	AC1	OUT	Async	Comparator output level	All channels
`0x24`	ADC0	RES	Sync	Result ready	All channels⁽¹⁾
`0x25`		SAMP		Sample ready
`0x26`		WCMP		Window compare match
`0x40`	PORTA	EVGEN0	Async	Pin level⁽²⁾	All channels
`0x41`	PORTA	EVGEN1	Async	Pin level⁽²⁾	All channels
`0x42`	PORTB⁽¹⁾	EVGEN0	Async	Pin level⁽²⁾	All channels
`0x43`	PORTB⁽¹⁾	EVGEN1	Async	Pin level⁽²⁾	All channels
`0x44`	PORTC	EVGEN0	Async	Pin level⁽²⁾	All channels
`0x45`	PORTC	EVGEN1	Async	Pin level⁽²⁾	All channels
`0x46`	PORTD	EVGEN0	Async	Pin level⁽²⁾	All channels
`0x47`	PORTD	EVGEN1	Async	Pin level⁽²⁾	All channels
`0x48`	PORTE⁽¹⁾	EVGEN0	Async	Pin level⁽²⁾	All channels
`0x49`	PORTE⁽¹⁾	EVGEN1	Async	Pin level⁽²⁾	All channels
`0x4A`	PORTF	EVGEN0	Async	Pin level⁽²⁾	All channels
`0x4B`	PORTF	EVGEN1	Async	Pin level⁽²⁾	All channels
`0x60`	USART0	XCK	Sync	Clock signal in SPI host mode and synchronous USART host mode	All channels
`0x61`	USART1
`0x62`	USART2⁽¹⁾
`0x68`	SPI0	SCK	Sync	SPI host clock signal	All channels
`0x80`	TCA0	OVF_LUNF	Sync	Overflow/Low byte timer underflow	All channels
`0x81`		HUNF	Sync	High byte timer underflow
`0x84`		CMP0_LCMP0	Sync	Compare channel 0 match/Low byte timer compare channel 0 match
`0x85`		CMP1_LCMP1	Sync	Compare channel 1 match/Low byte timer compare channel 1 match
`0x86`		CMP2_LCMP2	Sync	Compare channel 2 match/Low byte timer compare channel 2 match
`0x88`	TCA1	OVF_LUNF	Sync	Overflow/Low byte timer underflow	All channels
`0x89`		HUNF	Sync	High byte timer underflow
`0x8C`		CMP0_LCMP0	Sync	Compare channel 0 match/Low byte timer compare channel 0 match
`0x8D`		CMP1_LCMP1	Sync	Compare channel 1 match/Low byte timer compare channel 1 match
`0x8E`		CMP2_LCMP2	Sync	Compare channel 2 match/Low byte timer compare channel 2 match
`0xA0`	TCB0	CAPT	Sync	CAPT interrupt flag set⁽³⁾	All channels
`0xA1`	TCB0	OVF	Sync	Counter overflow	All channels
`0xA2`	TCB1	CAPT	Sync	CAPT interrupt flag set⁽³⁾	All channels
`0xA3`	TCB1	OVF	Sync	Counter overflow	All channels
`0xA4`	TCB2	CAPT	Sync	CAPT interrupt flag set⁽³⁾	All channels
`0xA5`	TCB2	OVF	Sync	Counter overflow	All channels
`0xA6`	TCB3	CAPT	Sync	CAPT interrupt flag set⁽³⁾	All channels
`0xA7`	TCB3	OVF	Sync	Counter overflow	All channels

Note:

Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section for details.
An event from the PORT pin will be zero if the input driver is disabled.
The operational mode of the timer decides when the CAPT flag is raised. Refer to the TCB section for details.