11.5.1 Control A
Name: | CTRLA |
Offset: | 0x00 |
Reset: | 0x00 |
Property: | Configuration Change Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMD[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 6:0 – CMD[6:0] Command
Write this bit field to enable or issue a command. The Chip Erase and EEPROM erase commands start when writing either command to the bit field. The other commands enable an erase or a write operation. These operations start when doing a store to the flash address that is being erased or written.
It is recommended to include a NOCMD or NOOP instruction when going from one command to the next to avoid Command Collision error being set (the ERROR bit field in NVMCTRL.STATUS).
The Configuration Change Protection key for self-programming (SPM) protects these bits.
Value | Name | Description |
---|---|---|
0x00 | NOCMD | No command |
0x01 | NOOP | No operation |
0x04 | FLPW | Flash Page Write |
0x05 | FLPERW | Flash Page Erase and Page Write |
0x08 | FLPER | Flash Page Erase |
0x09 | FLMPER2 | Flash 2-page Erase Enable |
0x0A | FLMPER4 | Flash 4-page Erase Enable |
0x0B | FLMPER8 | Flash 8-page Erase Enable |
0x0C | FLMPER16 | Flash 16-page Erase Enable |
0x0D | FLMPER32 | Flash 32-page Erase Enable |
0x0F | FLPBCLR | Flash Page Buffer Clear |
0x14 | EEPW | EEPROM Page Write |
0x15 | EEPERW | EEPROM Page Erase and Page Write |
0x17 | EEPER | EEPROM Page Erase |
0x1F | EEPBCLR | EEPROM Page Buffer Clear |
0x20 | CHER | Erase Flash and EEPROM. EEPROM is skipped if the EESAVE fuse is set (UPDI access only). |
0x30 | EECHER | EEPROM Erase |
Other | - | Reserved |