2.5.2 Implementation Example for DDR3L

Figure 2-7. DDR Controller Configuration

In the above figure, the data bits connected to the DDR3L memory appear to be scrambled. This is called “bit swapping” and was done on purpose to ease up the layout routing. Refer to 4.1 Bit and Byte Swapping.

Make sure to define the Clock and DQS signals as differentials with a 100-ohm differential characteristic impedance, in order to export the information to the PCB and route them coupled as required.

Note: Zentel’s DDR3L SDRAM part numbers A3T1GF40CBF and A3T2GF40CBF have been successfully tested on evaluation board.