2.2.1 Abbreviations and Acronyms

Table 2-1. Abbreviations and Acronyms
Abbreviation	Description
ADC	Analog-to-Digital Converter of the AFE, consisting of a PGA, a Δ/Σ modulator, and followed by an integrated sinc decimation filter.
AFE	Analog Front End.
BAMS	Binary Angular Measurement System. Angles are normalized to the binary range [-1.0000, +0.9999] k, where k may represent any convenient scale, such as 180°, or π-radians. In this metering discussion, all angles are drawn as if vectors starting to 0° (3 o’clock position) and rotating counter-clockwise for positive phase increases. Using BAMS allows for graceful rollover from ±180º to ∓180º without edge-effects.
Δ/Σ ADC	Delta-Sigma Analog-to-Digital Converter, an over-sampled converter with noise shaping.
CT	Current Transformer sensor.
DB	Demo Board.
DNP	Do Not Populate.
DSP	Digital Signal Processor.
GPGA	Gain selected for use in the ADC front end.
GPIO	General Purpose Input/Output.
Kh	Watt-hour meter constant for electro-mechanical meters, defines an amount of energy indicated by one (1) pulse generated by the meter and does not usually apply to solid-state meters.
Kt	Watt-hour meter test constant for solid-state meters, defines an amount of energy indicated by one (1) optical pulse generated by the meter and does not usually apply to electro-mechanical meters.
LCD	Liquid Crystal Display.
MCU	Microcontroller Unit.
MSB	Most Significant Bit, the left-most bit of a binary number.
N	The number of samples in any one measurement interval. This number may vary for each measurement interval.
NA	Not Available.
OSR	Over Sample Rate.
PGA	Programmable Gain Amplifier: The ADC channels could have an internal, selectable, programmable gain amplifier that can provide an additional analog gain equal to GPGA.
SDK	Software Development Kit.
SoC	System-on-Chip.
TOU	Time of Use.
VP, VP-M	Voltage potential: VP is the voltage measured from node P to an implied neutral reference voltage. VP-M is the voltage measured from node P to node M, where a positive voltage is indicative of a voltage rise from node M to node P. All phase diagrams are drawn as if mathematical vectors starting at 0° (3 o’clock) and rotating counterclockwise for positive phase increases, with 90° being at 12 o’clock, 180° at 9 o’clock and 270° at 6 o’clock.
Qformat	To prevent ambiguity, this document uses the following definition of Qformat numbers, being a fixed-point number format representing both integer and fractional numbers, and may be unsigned (uQm.n) or signed (sQm.n). Unsigned Qformat numbers: An (m+n)-bit unsigned number is designated uQm.n. It occupies (m+n) bits and is stored as an unsigned fixed-point binary number. An unsigned uQm.n number may represent numbers in the range: [0, +(2m - 2-n)]. Signed Qformat numbers: An (m+n+1)-bit signed number is designated sQm.n. It occupies (m+n+1) bits and is stored as a signed fixed-point binary number, where the MSB is used as a sign bit. A signed sQm.n number may represent numbers in the range: [-(2m), +(2m - 2-n)]]. For example, an 8-bit sQ4.3 format number has one (1) sign bit, four (4) bits to the left of the binary point and three (3) bits to the right of the binary point and may be used to represent numbers in the range: [-(24), +(24 - 2-3)]] = [-16, +15.875]. To convert a sQm.n format number to a decimal equivalent, divide the equivalent twos-complement binary number by 2n. For example: an 8-bit signed sQ2.5 number: [0b0100 0001] = 65/(25) = 2.03125, an 8-bit [0b1100 0001] = -63/(25) = -1.96875. To convert a decimal number into a sQm.n format number, multiply by 2n and convert to a signed two’s-complement (m+n+1)-bit number. For example: -7.33 => sQ3.4: (-7.33)*(24) = -117 => -[0b0111 0101] => [0b1000 1011]. Example-1: sQ1.14 A signed 16-bit number, having 1 sign bit, 1 integer bit to the left of the binary point, and 14 mantissa bits to the right of the binary point that can represent numbers in the range: [-2.0, +1.999938965]. Example-2: uQ2.14 An unsigned 16-bit number, having no sign bit, 2 integer bits to the left of the binary point and 14 mantissa bits to the right of the binary point that can represent numbers in the range: [0, +3.999938965].

ADC

Analog-to-Digital Converter of the AFE, consisting of a PGA, a Δ/Σ modulator, and followed by an integrated sinc decimation filter.

AFE

Analog Front End.

BAMS

Binary Angular Measurement System. Angles are normalized to the binary range [-1.0000, +0.9999] k, where k may represent any convenient scale, such as 180°, or π-radians. In this metering discussion, all angles are drawn as if vectors starting to 0° (3 o’clock position) and rotating counter-clockwise for positive phase increases.

Using BAMS allows for graceful rollover from ±180º to ∓180º without edge-effects.

Δ/Σ ADC

Delta-Sigma Analog-to-Digital Converter, an over-sampled converter with noise shaping.

CT

Current Transformer sensor.

DB

Demo Board.

DNP

Do Not Populate.

DSP

Digital Signal Processor.

GPGA

Gain selected for use in the ADC front end.

GPIO

General Purpose Input/Output.

Kh

Watt-hour meter constant for electro-mechanical meters, defines an amount of energy indicated by one (1) pulse generated by the meter and does not usually apply to solid-state meters.

Kt

Watt-hour meter test constant for solid-state meters, defines an amount of energy indicated by one (1) optical pulse generated by the meter and does not usually apply to electro-mechanical meters.

LCD

Liquid Crystal Display.

MCU

Microcontroller Unit.

MSB

Most Significant Bit, the left-most bit of a binary number.

N

The number of samples in any one measurement interval. This number may vary for each measurement interval.

NA

Not Available.

OSR

Over Sample Rate.

PGA

Programmable Gain Amplifier: The ADC channels could have an internal, selectable, programmable gain amplifier that can provide an additional analog gain equal to GPGA.

SDK

Software Development Kit.

SoC

System-on-Chip.

TOU

Time of Use.

VP, VP-M

Voltage potential: VP is the voltage measured from node P to an implied neutral reference voltage.

VP-M is the voltage measured from node P to node M, where a positive voltage is indicative of a voltage rise from node M to node P.

All phase diagrams are drawn as if mathematical vectors starting at 0° (3 o’clock) and rotating counterclockwise for positive phase increases, with 90° being at 12 o’clock, 180° at 9 o’clock and 270° at 6 o’clock.

Qformat

To prevent ambiguity, this document uses the following definition of Qformat numbers, being a fixed-point number format representing both integer and fractional numbers, and may be unsigned (uQm.n) or signed (sQm.n).

Unsigned Qformat numbers: An (m+n)-bit unsigned number is designated uQm.n. It occupies (m+n) bits and is stored as an unsigned fixed-point binary number. An unsigned uQm.n number may represent numbers in the range: [0, +(2m - 2-n)].

Signed Qformat numbers: An (m+n+1)-bit signed number is designated sQm.n. It occupies (m+n+1) bits and is stored as a signed fixed-point binary number, where the MSB is used as a sign bit. A signed sQm.n number may represent numbers in the range: [-(2m), +(2m - 2-n)]].

For example, an 8-bit sQ4.3 format number has one (1) sign bit, four (4) bits to the left of the binary point and three (3) bits to the right of the binary point and may be used to represent numbers in the range:

[-(24), +(24 - 2-3)]] = [-16, +15.875].

To convert a sQm.n format number to a decimal equivalent, divide the equivalent twos-complement binary number by 2n. For example: an 8-bit signed sQ2.5 number: [0b0100 0001] = 65/(25) = 2.03125, an 8-bit [0b1100 0001] = -63/(25) = -1.96875.

To convert a decimal number into a sQm.n format number, multiply by 2n and convert to a signed two’s-complement (m+n+1)-bit number. For example: -7.33 => sQ3.4: (-7.33)*(24) = -117 => -[0b0111 0101] => [0b1000 1011].

Example-1: sQ1.14

A signed 16-bit number, having 1 sign bit, 1 integer bit to the left of the binary point, and 14 mantissa bits to the right of the binary point that can represent numbers in the range: [-2.0, +1.999938965].

Example-2: uQ2.14

An unsigned 16-bit number, having no sign bit, 2 integer bits to the left of the binary point and 14 mantissa bits to the right of the binary point that can represent numbers in the range: [0, +3.999938965].