1.8.1 The Buffer Full (BF) Bit or MSSP Interrupt Flag (SSPIF) Bit Becomes Set Half of a SCK Cycle Early
When the MSSP is used in SPI Master mode and the CKE bit is clear (CKE = 0), the
Buffer Full (BF) bit and the MSSP Interrupt Flag (SSPIF) bit becomes set half an SCK
cycle early. If the user software immediately reacts to either of the bits being set, a
write collision may occur as indicated by the WCOL bit being set.
Work around
To avoid a write collision, one of the following methods should be used:
Method 1:
Add a software delay of one SCK period after detecting the completed transfer (the BF bit or SSPIF bit becomes set) and prior to writing to the SSPBUF register. Verify the WCOL bit is clear after writing to SSPBUF. If the WCOL bit is set, clear the bit in software and rewrite the SSPBUF register.
Method 2:
As part of the MSSP initialization procedure, set the CKE bit (CKE =
1).
Affected Silicon Revisions
| A1 | A2 | A3 | |||||
| X | X | X |