Silicon Issue Summary
| Module | Feature | Item No. | Issue Summary | Affected Revisions | ||
|---|---|---|---|---|---|---|
| A1 | A2 | A3 | ||||
| Analog-to-Digital Converter (ADC) | ADC Conversion | 1.1.1 | ADC Conversion May Not Complete | X | ||
| Enhanced Capture Compare PWM (ECCP) | Enhanced PWM | 1.2.1 | PWM 0% Duty Cycle Direction Change | X | ||
| Enhanced PWM | 1.2.2 | PWM 0% Duty Cycle Port Steering | X | |||
| Timer1 | Timer1 Gate Toggle Mode | 1.3.1 | T1 Gate Flip-Flop Does Not Clear | X | ||
| In-Circuit Serial Programming™ (ICSP™) | Low-Voltage Programming | 1.4.1 | Bulk Erase Not Available with LVP | X | ||
| Oscillator (OSC) | Clock Switching | 1.5.1 | Clock Switching Can Cause a Single Corrupted Instruction | X | X | |
| Oscillator Start-Up Timer (OSTS) Bit | 1.5.2 | OSTS Bit Remains Set | X | X | ||
| Oscillator Start-Up Timer (OSTS) Bit | 1.5.3 | OSTS Bit Remains Clear | X | X | X | |
| Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) | Auto-Baud Detect | 1.6.1 | Auto-Baud Detect May Store Incorrect Count Value in the SPBRG Registers | X | X | |
| Brown-Out Reset (BOR) | Wake-Up from Sleep | 1.7.1 | Device Resets on Wake-Up from Sleep (PIC16LF1938/1939 devices only) | X | X | |
| Master Synchronous Serial Port (MSSP) | SPI Master Mode | 1.8.1 | The Buffer Full (BF) Bit or MSSP Interrupt Flag (SSPIF) Bit Becomes Set Half of a SCK Cycle Early | X | X | X |
|
Note: Only those issues indicated in the last column
apply to the current silicon revision.
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