25.5.10 Status

Name: STATUS
Offset: 0x0E
Reset: 0x00
Property: -

Bit 76543210 
 PWMACTB PWMACTA     CMDRDYENRDY 
Access R/WR/WRR 
Reset 0000 

Bit 7 – PWMACTB PWM Activity on B

This bit is set by hardware each time the WOB output toggles from ‘0’ to ‘1’ or from ‘1’ to ‘0’.

This status bit must be cleared by software by writing a ‘1’ to it before new PWM activity can be detected.

Bit 6 – PWMACTA PWM Activity on A

This bit is set by hardware each time the WOA output toggles from ‘0’ to ‘1’ or from ‘1’ to ‘0’.

This status bit must be cleared by software by writing a ‘1’ to it before new PWM activity can be detected.

Bit 1 – CMDRDY Command Ready

This status bit tells when a command is synced to the TCD domain, and the system is ready to receive new commands.

The following actions clear the CMDRDY bit:
  1. TCDn.CTRLE SYNCEOC strobe.
  2. TCDn.CTRLE SYNC strobe.
  3. TCDn.CTRLE RESTART strobe.
  4. TCDn.CTRLE SCAPTUREA Capture A strobe.
  5. TCDn.CTRLE SCAPTUREB Capture B strobe.
  6. TCDn.CTRLC AUPDATE written to ‘1’ and writing to the TCDn.CMPBCLRH register.

Bit 0 – ENRDY Enable Ready

This status bit tells when the ENABLE value in TCDn.CTRLA is synced to the TCD domain and is ready to be written to again.

The following actions clear the ENRDY bit:
  1. Writing to the ENABLE bit in TCDn.CTRLA.
  2. TCDn.CTRLE DISEOC strobe.
  3. Going into BREAK in an On-Chip Debugging (OCD) session while the Debug Run (DBGCTRL) bit in TCDn.DBGCTRL is ‘0’.