4.1 ADC Clock

Before using the ADC controller, its GCLK must be enabled in the Power Management Controller (PMC). To reach the maximum sampling rate (1 MS/s), the ADCCLK frequency, derived from the GCLK, must be 20 MHz:

f_{A D C C L K} = \frac{f_{G C L K}}{A D C_M R . P R E S C A L} = 20 M H z

f_ADCCLK can be set to a value lower than 20 MHz if required by the application (for example, if one of the channels used in the application needs a very long tracking time).