6.4.4 NVMREG Erase of Program Memory

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write to program memory. To erase a program memory row:
  1. Clear the NVMREGS bit of the NVMCON1 register to erase program memory locations, or set the NMVREGS bit to erase User ID locations.
  2. Write the desired address into the NVMADRH:NVMADRL register pair.
  3. Set the FREE and WREN bits of the NVMCON1 register.
  4. Perform the unlock sequence as described in the “NVM Unlock Sequence” section.

If the program memory address is write-protected, the WR bit will be cleared and the erase operation will not take place.

While erasing program memory, CPU operation is suspended, and resumes when the operation is complete. Upon completion, the NVMIF is set, and an interrupt will occur if the NVMIE bit is also set.

Write latch data is not affected by erase operations, and WREN will remain unchanged.

Figure 6-3. NVM Erase Flowchart
Note: See the previous figure.

Erasing One Row of Program Flash Memory

   ; This sample row erase routine assumes the following:
   ; 1.A valid address within the erase row is loaded 
   ; in variables ADDRH:ADDRL
   ; 2.ADDRH and ADDRL are located in common RAM 
   ; (locations 0x70 - 0x7F)

    BANKSEL    NVMADRL
    MOVF       ADDRL,W           ; Load lower 8 bits of
    MOVWF      NVMADRL           ; erase address boundary
    MOVF       ADDRH,W           ; Load upper 6 bits
    MOVWF      NVMADRH           ; of erase address boundary
    BCF        NVMCON1,NVMREGS   ; Choose PFM memory area
    BSF        NVMCON1,FREE      ; Specify an erase operation
    BSF        NVMCON1,WREN      ; Enable writes
    BCF        INTCON,GIE        ; Disable interrupts during 
                                 ; unlock sequence

    ; ------------------REQUIRED UNLOCK SEQUENCE:-----------------
    MOVLW       0x55              ; Load 0x55 to get ready for 
                                  ; unlock sequence
    MOVWF       NVMCON2           ; First step, load 0x55 into NVMCON2
    MOVLW       0xAA              ; Second step, load 0xAA into W
    MOVWF       NVMCON2           ; Third step, load 0xAA into NVMCON2
    BSF         NVMCON1,WR        ; Final step, set WR bit
	
    ; -------------------ERASE IS COMPLETE----------------------
    BSF         INTCON,GIE        ; Re-enable interrupts
    BCF         NVMCON1,WREN      ; Disable writes
Table 6-1. NVM Organization and Access Information
Host ValuesNVMREG AccessFSR Access
Memory FunctionMemory TypeProgram Counter (PC)ICSP™ AddressNVMREGS bit (NVMCON1)NVMADR[14:0]Allowed OperationsFSR AddressFSR Programming Access
RESET VECTORProgram Flash Memory0x00000x000000x0000READ/WRITE0x8000READ ONLY
USER MEMORY0x00010x000100x00010x8001
0x00030x00030x00030x8003
INT VECTOR0x00040x000400x00040x8004
USER MEMORY0x00050x000500x00050x8005
0x7FFF(1)0x7FFF(1)0x7FFF(1)0xFFFF
USER IDProgram Flash MemoryNO PC ACCESS0x800010x0000READ/WRITENO ACCESS
0x80030x0003
Reserved———0x0004—
REV IDHC0x800510x0005READ
DEVICE ID0x800610x0006
CONFIG1FUSE0x800710x0007READ/WRITE
CONFIG20x800810x0008
CONFIG30x800910x0009
CONFIG40x800A10x000A
CONFIG50x800B10x000B
DIA and DCIPFM0x810010x0100READ
0x82FF10x02FF
USER MEMORYEEPROM0xF00010x7000READ/WRITE0x7000READ ONLY
0xF0FF0x70FF0x70FF
Note:
  1. The maximum Program Flash Memory address for the PIC16(L)F184XX family is 0x7FFF.