4 Timer/Counter D (TCD)

TCD is a 12-bit timer optimized for generating complex PWM waveforms, such as half-bridge and full-bridge outputs. There are two comparators inside TCD: CMPA and CMPB. Each comparator has a SET value and a CLR value. When the count hits SET, the output is active. Then, when CLR is reached, the output is deactivated.

TCD supports four operation modes: One Ramp, Two Ramp, Four Ramp, and Dual-Slope. These names represent the number of cycles the counter goes through. Four Ramp mode goes through four cycles, resetting on CMPASET, CMPACLR, CMPBSET, and CMPBCLR, in that order. Two Ramp mode goes through two cycles, resetting on CMPACLR and CMPBCLR, in that order. One Ramp mode resets only on the CMPBCLR. Finally, Dual-Slope mode counts up to CMPBCLR and then counts down to zero. The graphic below has each ramp end at the same y-position for visual purposes. However, they will vary when the values aren’t equal. Additionally, values not shown ( e.g., CMPASET CMPASET in 1 Ramp mode) are still active but do not play a role in the period.

Through the EVSYS, TCD also supports input blanking, digital filtering, and several fault modes for clearing the output and/or suspending the count. TCD can also be used for input captures. Additionally, you can use TCD with the PLL (Phase-Locked Loop), which enables TCD to operate at a frequency higher than the primary clock.