41.4.16 SPI Mode Requirements

Table 41-22. SPI Mode
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Characteristic Min. Typ. † Max. Units Conditions
SP70*

TSSL2SCH,

TSSL2SCL

SDO to SCK↓ or SCK↑ input 2.25*TCY ns
SP71* TSCH SCK output high time TCY + 20 0.5 TSCK + 12 ns
SP72* TSCL SCK output low time TCY + 20 0.5 TSCK + 12 ns
SP73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge 100 ns
SP74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge 100 ns
Hold time of SDI data input to final SCK 0.5 TSCK ns CKE = 0,

SMP = 1

SP75* TDOR SDO data output rise time 25 50 ns CL = 50 pF
SP76* TDOF SDO data output fall time 10 25 ns CL = 50 pF
SP77* TSSH2DOZ SS ↑ to SDO output high-impedance 10 50 ns
SP78* TSCR SCK output rise time 25 50 ns CL = 50 pF
SP79* TSCF SCK output fall time 10 25 ns CL = 50 pF
SP80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK edge 145 ns CL = 50 pF
SP81*

TDOV2SCH,

TDOV2SCL

SDO data output valid to first SCK edge 1 TCY ns

CL = 50 pF

CKE = 1

SP82* TSSL2DOV SDO data output valid after SS↓ edge 50 ns CL = 20 pF
SP83*

TSCH2SSH,

TSCL2SSH

SS ↑ after last SCK edge 1.5 TCY + 40 ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. SMP bit in the SSPxSTAT register must be set and the slew rate control must be disabled on the clock and data pins (clear the corresponding bits in SLRCONx register) for SPI to operate over 4 MHz.
Figure 41-15. SPI Host Mode Timing (CKE = 0, SMP = 0)
Note: Refer to the “Load Conditions” figure for load conditions.
Figure 41-16. SPI Host Mode Timing (CKE = 1, SMP = 1)
Note: Refer to the “Load Conditions” figure for load conditions.
Figure 41-17. SPI Client Mode Timing (CKE = 0)
Note: Refer to the “Load Conditions” figure for load conditions.
Figure 41-18. SPI Client Mode Timing (CKE = 1)
Note: Refer to the “Load Conditions” figure for load conditions.