41.4.1 External Clock/Oscillator Timing Requirements

Figure 41-4. Clock Timing

Table 41-7.
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
ECL Oscillator
OS1	F_ECL	Clock Frequency	—	—	1	MHz
OS2	T_{ECL_DC}	Clock Duty Cycle	40	—	60	%
ECH Oscillator
OS5	F_ECH	Clock Frequency	—	—	32	MHz	V_DD ≥ 2.7V
OS5	F_ECH	Clock Frequency	—	—	16	MHz	V_DD < 2.7V
OS6	T_{ECH_DC}	Clock Duty Cycle	40	—	60	%
Secondary Oscillator
OS10	F_SEC	Clock Frequency	—	32.768	—	kHz	(Note 4)
System Oscillator
OS20	F_OSC	System Clock Frequency	—	—	32	MHz	(Note 2, Note 3)
OS21	F_CY	Instruction Frequency	—	F_OSC/4	—	MHz
OS22	T_CY	Instruction Period	125	1/F_CY	—	ns
Note: Instruction cycle period (T_CY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. The system clock frequency (F_OSC) is selected by the “main clock switch controls” as described in the “Power Saving Operation Modes” section. The system clock frequency (F_OSC) must meet the voltage requirements defined in the “Standard Operating Conditions” section.