15.3.3 NVMCON1

Nonvolatile Memory Control 1 Register
Note:
  1. Bit is undefined while WR = 1.
  2. Bit must be cleared by software; hardware will not clear this bit.
  3. Bit may be written to ‘1’ by the user to implement test sequences.
  4. This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section.
  5. Operations are self-timed and the WR bit is cleared by hardware when complete.
  6. Once a write operation is initiated, setting this bit to zero will have no effect.
Name: NVMCON1
Address: 0x1C90

Bit 76543210 
  NVMREGSLWLOFREEWRERRWRENWRRD 
Access R/WR/WR/S/HCR/W/HSR/WR/S/HCR/S/HC 
Reset 0000000 

Bit 6 – NVMREGS NVM Region Selection

ValueDescription
1 Access DFM (EEPROM), DIA, DCI, Configuration, User ID, Revision ID, and Device ID Registers
0 Access Program Flash Memory

Bit 5 – LWLO Load Write Latches Only

ValueNameDescription
1 When FREE = 0 The next WR command updates the write latch for this word within the row; no memory operation is initiated
0 When FREE = 0 The next WR command writes data or erases
- Otherwise: This bit is ignored

Bit 4 – FREE Program Flash Memory Erase Enable

ValueDescription
1 Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated address is erased (to all 1s) to prepare for writing
0 The next WR command writes without erasing

Bit 3 – WRERR

Write-Reset Error Flag(1,2,3)
ValueDescription
1 A write operation error has occurred
0 All write operations have completed normally

Bit 2 – WREN Program/Erase Enable

ValueDescription
1 Allows program/erase cycles
0 Inhibits programming/erasing of program Flash

Bit 1 – WR  Write Control(4,5,6)

ValueDescription
1 Initiates the program/erase operation at the corresponding NVM location
0 NVM program/erase operation is complete and inactive

Bit 0 – RD Read Control

ValueDescription
1 Initiates a read at address = NVMADR
0 NVM read operation is complete and inactive
Bit is undefined while WR = 1. Bit must be cleared by software; hardware will not clear this bit. Bit may be written to ‘1’ by the user to implement test sequences. This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section. Operations are self-timed and the WR bit is cleared by hardware when complete. Once a write operation is initiated, setting this bit to zero will have no effect.