1 Peripheral Overview: Analog-to-Digital Converter with Programmable Gain Amplifier

The ADC peripheral on the AVR EB family of microcontrollers features the following characteristics:

  • 12-Bit Resolution
    • Up to 17 bits with oversampling
  • Conversion Rate Up to 300 ksps at 12-Bit Resolution
  • Up to 24 Inputs
  • Differential and Single-Ended Conversion
  • Programmable Gain Amplifier from 1x to 16x
  • Input Voltage Range from -100 mV to VDD+100 mV
  • Multiple Internal ADC Reference Voltages
    • VDD
    • 1.024V
    • 2.048V
    • 2.500V
    • 4.096V
  • External Reference Input
  • Single and Free-Running Conversions
  • Series and Burst Accumulation Modes
  • Accumulation of Up to 1024 Conversions
  • Left or Right Adjusted Result
  • Interrupts on Conversion Complete
  • Optional Event Triggered Conversion
  • Configurable Window Comparator
Figure 1-1. ADC Block Diagram

The ADC supports six different operation modes, with differential and single-ended conversions possible for each mode:

  • Single mode – Single conversion per trigger, with 8- or 12-bit conversion output
  • Series Accumulation mode – One conversion per trigger, with an accumulation of n samples
  • Burst Accumulation mode – A burst of n samples accumulated as fast as possible after a single trigger

In Series and Burst modes, the SAMPNUM bit field in the Control F register controls how many samples to accumulate. This hardware accumulation feature acts as a noise filter, allowing for more accurate sampling of the input signal. The noise reduction comes at the expense of total conversion time, which the application must take into consideration.

An ADC conversion is started by one of the following triggers, depending on the configuration of the START bit field in the Command register:

  • Writing the IMMEDIATE value to the START bit field
  • Receiving an event input
  • Writing to one of the input multiplexer registers

The Result Ready interrupt flag in the Interrupt Flags register shows if a conversion or accumulation has finished. This flag also triggers the corresponding interrupt if enabled in the Interrupt Control register.

In the default configuration, the PGA is disabled, and the input signals are sampled directly into the conversion state without internal amplification. Depending on the input signal properties, it can be desirable to configure the internal PGA stage to amplify the signal. In comparison to external amplifiers, the internal PGA has several desirable properties:

  • Small bill of materials
  • Low number of pins required
  • Firmware selectable gain with input multiplexing for flexible and feature-rich applications
  • Non-inverting amplification maintains signs/logic structure in firmware when the application requires to operate with PGA turned on and off

The user must consider the following effects when using the PGA:

  • The input signal is amplified with the natural side effects of an additional amplification stage (input noise, offset and gain error) and possible saturation
  • The maximum conversion rate is slower because the ADC needs to sample the PGA
  • Power consumption is slightly increased
  • Depending on the sampling mode, the relative timing of the conversions is altered

The PGA is enabled by setting the PGAEN bit and configuring the GAIN bit field in the PGA Control register. The VIA bit fields in the Positive and Negative Input Multiplexer registers determine whether the input signal is connected via the PGA or is fed straight to the conversion stage. The VIA bits are shared, so a value written to the VIA bit field in any Input Multiplexer register updates both.