7.5 Write Protection

The AT24C512C utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory contents when the WP pin is at V_CC(or a valid V_IH). No write protection will be set if the WP pin is at GND or left floating.

Table 7-1. AT24C512C Write-Protect Behavior
WP Pin Voltage	Part of the Array Protected
V_CC	Full Array
GND	None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not alter or interrupt the execution of the write cycle.

If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the device address, word address and data bytes. However, no write cycle will occur when the Stop condition is issued. The device will immediately be ready to accept a new read or write command.