In this design, The XCVR block manages high-speed serial data reception from the host PC, converting it into parallel data for processing. This parallel data is then received and decoded by the DisplayPort Rx block, which initially stores the frame data in LSRAM line buffers. Due to the significant memory required to store an entire video frame, the frame data is transferred to DDR4 memory. This transfer is efficiently managed using a DDR AXI4 Arbiter IP block and a DDR4 controller. Once stored, the video frame data is read from DDR4 memory and processed by the onboard HDMI 2.0 IP. Finally, the HDMI IP outputs the video to the connected HDMI monitor, ensuring smooth and reliable display of the video content.
The following figure shows a high-level block diagram of the design.Figure 3-1. Block Diagram
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