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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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Product Pages
SAMA7G54
Home
2
CPU and Interconnect
2.2
System Interconnect and Security (SIS)
2.2.4
TrustZone Security Management
2.2.4.7
TrustZone AES Bridge Address Space Controller (TZAESBASC)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.2.1
System Bus and Interconnect
2.2.2
System Interconnect Overview
2.2.3
Quality of Service (QoS) Overview
2.2.4
TrustZone Security Management
2.2.4.1
TrustZone System Overview
2.2.4.2
Core Security Extensions Overview
2.2.4.3
TrustZone Peripheral Manager (TZPM)
2.2.4.4
AHB Matrix (MATRIX)
2.2.4.5
TrustZone Address Space Controller (TZC-400)
2.2.4.6
Programmable IO Controller (PIOC)
2.2.4.7
TrustZone AES Bridge Address Space Controller (TZAESBASC)
2.2.4.7.1
Function
2.2.4.7.2
Encryption Behavior
2.2.4.7.3
Access Denials
2.2.4.7.4
NAND Flash
2.2.4.8
TrustZone Watchdog
2.2.4.9
Security Module (SECUMOD)
2.2.4.10
Extended DMA Controller (XDMAC)
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
2.2.4.7 TrustZone AES Bridge Address Space Controller (TZAESBASC)
