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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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Product Pages
SAMA7G54
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9
Connectivity Subsystem
9.6
Controller Area Network (MCAN)
9.6.5
Functional Description
9.6.5.7
Message RAM
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
9.1
Overview
9.2
Gigabit
Ethernet MAC (GMAC)
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.4
Quad Serial Peripheral Interface (QSPI)
9.5
Secure Digital MultiMedia Card Controller (SDMMC)
9.6
Controller Area Network (MCAN)
9.6.1
Description
9.6.2
Embedded Characteristics
9.6.3
Block Diagram
9.6.4
Product Dependencies
9.6.5
Functional Description
9.6.5.1
Operating Modes
9.6.5.2
Timestamp Generation
9.6.5.3
Timeout Counter
9.6.5.4
Rx Handling
9.6.5.5
Tx Handling
9.6.5.6
FIFO Acknowledge Handling
9.6.5.7
Message RAM
9.6.5.7.1
Message RAM Configuration
9.6.5.7.2
Rx Buffer and FIFO Element
9.6.5.7.3
Tx Buffer Element
9.6.5.7.4
Tx Event FIFO Element
9.6.5.7.5
Standard Message ID Filter Element
9.6.5.7.6
Extended Message ID Filter Element
9.6.5.8
Hardware Reset Description
9.6.5.9
Access to Reserved Register Addresses
9.6.6
Register Summary
9.7
Timer Counter (TC)
9.8
Pulse Width Modulation Controller (PWM)
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
9.6.5.7 Message RAM
