Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Search
Product Pages
SAMA7G54
Home
9
Connectivity Subsystem
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.3.8
SPI Functional Description
9.3.8.3
Host Mode Operations
9.3.8.3.1
Host Mode Block Diagram
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
9.1
Overview
9.2
Gigabit
Ethernet MAC (GMAC)
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.3.1
Description
9.3.2
Embedded Characteristics
9.3.3
Block Diagram
9.3.4
I/O Lines Description
9.3.5
Product Dependencies
9.3.6
Register Accesses
9.3.7
USART Functional Description
9.3.8
SPI Functional Description
9.3.8.1
Modes of Operation
9.3.8.2
Data Transfer
9.3.8.3
Host Mode Operations
9.3.8.3.1
Host Mode Block Diagram
9.3.8.3.2
Host Mode Flowchart
9.3.8.3.3
Clock Generation
9.3.8.3.4
Transfer Delays
9.3.8.3.5
Peripheral Selection
9.3.8.3.6
SPI Direct Access Memory Controller (DMAC)
9.3.8.3.7
Peripheral Chip Select Decoding
9.3.8.3.8
Peripheral Deselection without
DMA
9.3.8.3.9
Peripheral Deselection with
DMA
9.3.8.3.10
Mode Fault Detection
9.3.8.4
SPI Client Mode
9.3.8.5
SPI Comparison Function on Received Character
9.3.8.6
SPI Asynchronous and Partial Wake-up
9.3.8.7
SPI FIFOs
9.3.8.8
SPI Register Write Protection
9.3.8.9
Local Loopback Test Mode
9.3.9
TWI Functional Description
9.3.10
Register Summary
9.4
Quad Serial Peripheral Interface (QSPI)
9.5
Secure Digital MultiMedia Card Controller (SDMMC)
9.6
Controller Area Network (MCAN)
9.7
Timer Counter (TC)
9.8
Pulse Width Modulation Controller (PWM)
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
9.3.8.3.1 Host Mode Block Diagram
Figure 9-73.
Host Mode Block Diagram
