32, 32 and
8 DMA Channels, Respectively, for XDMAC0, XDMAC1 and XDMAC2
61 Hardware Requests
8448, 8448 and 2112 bytes Embedded FIFO, Respectively, for
XDMAC0, XDMAC1 and XDMAC2
Supports Peripheral-to-Memory, Memory-to-Peripheral, or Memory-to-Memory Transfer Operations
Peripheral DMA Operation Runs on Bytes (8-bit), Half-Word (16-bit) and Word (32-bit)
Memory DMA Operation Runs on Bytes (8 bit), Half-Word (16-bit), Word (32-bit) and Double-Word (64-bit)
Supports Hardware and Software Initiated Transfers
Supports Linked List Operations
Supports Incrementing or Fixed Addressing Mode
Supports Programmable Independent Data Striding for Source and
Destination
Supports Programmable Independent Microblock Striding for Source
and Destination
Configurable Priority Group and Arbitration Policy
Programmable AXI Burst Length
Configuration Interface on Peripheral Bus
XDMAC Architecture Includes Multiport FIFO
Supports Multiple View Channel Descriptor
Automatic Flush of Channel Trailing Bytes
Automatic Coarse-Grain and Fine-Grain Clock Gating
Hardware Acceleration of Memset Pattern
Supports Configurable Quality of Service per
Channel
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
