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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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Product Pages
SAMA7G54
Home
2
CPU and Interconnect
2.2
System Interconnect and Security (SIS)
2.2.3
Quality of Service (QoS) Overview
2.2.3.2
DMA
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.2.1
System Bus and Interconnect
2.2.2
System Interconnect Overview
2.2.3
Quality of Service (QoS) Overview
2.2.3.1
Cortex-A7 CPU
2.2.3.2
DMA
2.2.3.2.1
DMA Per Queue Outstanding Capabilities
2.2.3.2.2
DMA Channel QoS
2.2.3.3
GMAC
2.2.3.4
SDMMC
2.2.3.5
ISC
2.2.3.6
AHB
2.2.3.7
UDDRC
2.2.4
TrustZone Security Management
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
2.2.3.2 DMA
