5.2.6.2 ADC Mode Register

This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.

Name:	ADC_MR
Offset:	0x04
Reset:	0x20000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	USEQ	ALWAYS1	TRANSFER[1:0]		TRACKTIM[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ANACH				STARTUP[3:0]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PRESCAL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		FWUP	SLEEP		TRGSEL[2:0]
Access		R/W	R/W		R/W	R/W	R/W
Reset		0	0		0	0	0

Bit 31 – USEQ User Sequence Enable

Value	Name	Description
0	NUM_ORDER	Normal mode: The controller converts channels in a simple numeric order depending only on the channel index.
1	REG_ORDER	User Sequence mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 and can be used to convert the same channel several times.

Bit 30 – ALWAYS1 Must always be written to 1

Bits 29:28 – TRANSFER[1:0] Transfer Time

Must be set to 2 to ensure the optimal transfer time.

Bits 27:24 – TRACKTIM[3:0] Tracking Time


ADC_EMR.TRACKX	TRACKTIM
ADC_EMR.TRACKX	0 to 3	4 to 14	15
0	6 × t_ADCCLK		7 × t_ADCCLK
1	6 × t_ADCCLK	([4 × (TRACKTIM + 1)] - 10) × t_ADCCLK
2	Not Applicable	([8 × (TRACKTIM + 1)] - 10) × t_ADCCLK
3	Not Applicable	([16× (TRACKTIM + 1)] - 10) × t_ADCCLK

Bit 23 – ANACH Analog Change

Value	Name	Description
0	NONE	No analog change on channel switching: DIFF0 is used for all channels.
1	ALLOWED	Allows different analog settings for each channel. See ADC_CCR.

Bits 19:16 – STARTUP[3:0] Start-Up Time

Value	Name	Description
0	SUT0	0 period of ADCCLK
1	SUT8	8 periods of ADCCLK
2	SUT16	16 periods of ADCCLK
3	SUT24	24 periods of ADCCLK
4	SUT64	64 periods of ADCCLK
5	SUT80	80 periods of ADCCLK
6	SUT96	96 periods of ADCCLK
7	SUT112	112 periods of ADCCLK
8	SUT512	512 periods of ADCCLK
9	SUT576	576 periods of ADCCLK
10	SUT640	640 periods of ADCCLK
11	SUT704	704 periods of ADCCLK
12	SUT768	768 periods of ADCCLK
13	SUT832	832 periods of ADCCLK
14	SUT896	896 periods of ADCCLK
15	SUT960	960 periods of ADCCLK

Bits 15:8 – PRESCAL[7:0] Prescaler Rate Selection

PRESCAL = (f_{peripheral clock}/ (2 × f_ADCCLK)) – 1.

Bit 6 – FWUP Fast Wakeup

Value	Name	Description
0	OFF	If SLEEP is 1, then both ADC core and reference voltage circuitry are off between conversions.
1	ON	If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is on between conversions and ADC core is off.

Bit 5 – SLEEP Sleep Mode

Value	Name	Description
0	NORMAL	Normal mode: The ADC core and reference voltage circuitry are kept on between conversions.
1	SLEEP	Sleep mode: The wake-up time can be modified by programming the FWUP bit.

Bits 3:1 – TRGSEL[2:0] Trigger Selection

The trigger selection can be performed only if ADC_TRGR.TRGMOD = 1, 2 or 3.

Value	Name	Description
0	ADC_TRIG0	ADTRG
1	ADC_TRIG1	TIOA0 TC0
2	ADC_TRIG2	TIOA1 TC0
3	ADC_TRIG3	TIOA2 TC0
4	ADC_TRIG4	TIOA0_TC1
5	ADC_TRIG5	ACC
6	ADC_TRIG6	PWM event line 0
7	ADC_TRIG7	RTCOUT0

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