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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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SAMA7G54
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9
Connectivity Subsystem
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.3.9
TWI Functional Description
9.3.9.6
TWI FIFOs
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
9.1
Overview
9.2
Gigabit
Ethernet MAC (GMAC)
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.3.1
Description
9.3.2
Embedded Characteristics
9.3.3
Block Diagram
9.3.4
I/O Lines Description
9.3.5
Product Dependencies
9.3.6
Register Accesses
9.3.7
USART Functional Description
9.3.8
SPI Functional Description
9.3.9
TWI Functional Description
9.3.9.1
Transfer Format
9.3.9.2
Modes of Operation
9.3.9.3
Host Mode
9.3.9.4
Multi-Host Mode
9.3.9.5
Client Mode
9.3.9.6
TWI FIFOs
9.3.9.6.1
Overview
9.3.9.6.2
Sending Data with FIFO Enabled
9.3.9.6.3
Receiving Data with FIFO Enabled
9.3.9.6.4
Sending/Receiving with FIFO Enabled in Client Mode
9.3.9.6.5
Clearing/Flushing FIFOs
9.3.9.6.6
TXRDY and RXRDY Behavior
9.3.9.6.7
TWI Single Data Access
9.3.9.6.8
TWI Multiple Data Access
9.3.9.6.9
Transmit FIFO Lock
9.3.9.6.10
FIFO Overflow/Underflow Error
9.3.9.6.11
FIFO Thresholds
9.3.9.6.12
FIFO Flags
9.3.9.7
TWI Comparison Function on Received Character
9.3.9.8
Sniffer Mode
9.3.9.9
TWI Register Write Protection
9.3.10
Register Summary
9.4
Quad Serial Peripheral Interface (QSPI)
9.5
Secure Digital MultiMedia Card Controller (SDMMC)
9.6
Controller Area Network (MCAN)
9.7
Timer Counter (TC)
9.8
Pulse Width Modulation Controller (PWM)
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
9.3.9.6 TWI FIFOs
