4.3.3.3 General Purpose Backup Register x [x=0..1]
This register can only be written if the WPEN bit is cleared in the System
Controller Write Protection Mode register (SYSC_WPMR).
These registers are reset at first power-up and on each loss of VBAT.
If
an event has been detected on WKUP pins enabled for tamper event detection in the RTC,
it is not possible to write to SYS_GPBRx as long as the event has not been cleared.
Name:
SYS_GPBRx
Offset:
0x08 + x*0x04 [x=0..1]
Reset:
0x00000000
Property:
R/W
Bit
31
30
29
28
27
26
25
24
GPBR_VALUE[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
GPBR_VALUE[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
GPBR_VALUE[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
GPBR_VALUE[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – GPBR_VALUE[31:0] Value of
SYS_GPBRx
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