5.3.7.7 ACC Analog Control Register
This register can only be written if the WPEN bit is cleared in ACC Write Protection Mode Register.
| Name: | ACC_ACR |
| Offset: | 0x94 |
| Reset: | 0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSEL | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – MSEL Masking Period Selection
| Value | Description |
|---|---|
| 0 |
Masks AC output for 16 peripheral clock periods after any write access in ACC_MR or ACC_CR. |
| 1 |
Masks AC output for 128 peripheral clock periods after any write access in ACC_MR or ACC_CR. |