| VDDIODDR | Power supply of memory interface | Power | – |
| DDR_VREF | Reference voltage | Input | – |
| DDR_ZQ | Calibration reference | Input | – |
| DDR_ODT | On-Die-Termination | Output | – |
| DDR_D[15:0] | Data bus | I/O | – |
| DDR_A[15:0] | Address bus | Output | – |
| DDR_DQM[1:0] | Data mask | Output | – |
| DDR_DQS[1:0] | Data strobe | I/O | – |
| DDR_DQSN[1:0] | Negative data strobe | I/O | – |
| DDR_CSN | Chip select | Output | Low |
| DDR_RESETN | DDR3 active low asynchronous reset | Output | Low |
| DDR_CLK, DDR_CLKN | Differential clock | Output | – |
| DDR_CKE | Clock enable | Output | High |
| DDR_RASN | Row signal | Output | Low |
| DDR_CASN | Column signal | Output | Low |
| DDR_WEN | Write enable | Output | Low |
| DDR_BA[2:0] | Bank Select | Output | – |
