2.2.2 System Interconnect Overview

The following table shows allowed paths (X).

Table 2-7. System Interconnections
UDDRC_P0 – MCK4UDDRC_P1 – MCK1UDDRC_P2 – MCK1UDDRC_P3 – MCK3UDDRC_P4 – MCK1OTPC – MCK0CPKCC RAM/ROM – MCK0APB0 – MCK0APB1 – MCK1APB2 – MCK1APB3 – MCK1APB4 – MXK1APB5 – MCK1APB6 – MCK1APB7 – MCK1USB_RAM – MCK1SRAM_P0 – MCK1SRAM_P1 – MCK1TZAESB – MCK1SMC – MKC1QSPI0 – MCK1QSPI1 – MCK1NFC_RAM – MCK1NFC_CMD – MCK1UHPHS_OHCI/EHCI – MCK1APB_DBG/APB_DBG_S – MCK1NICGPV – MCK1CSI2DC_META – MCK1ROM/ ECC_ROM – MCK0
TrustZone Management Location(1)TZCTZCTZCTZCTZCAS(2)AS (2)AS(2)TZPMTZPMTZPMTZPMTZPMTZPMTZPMMATRIXMATRIXMATRIXTZAESBAS -CTZPMMATRIXMATRIXMATRIXMATRIXMATRIXMATRIXMATRIXAS(2)MCK1MCK0
CA7 – MCK4Supervi-sor mode or CP15X––––XXXXXXXXXXXX–XXXXXXXXX–X
XDMAC0–MCK1XDMAC0––X–––––XXXX–X–––XXXXXX––––––
XDMAC1–MCK1XDMAC1––X–––––XXXX–X–––XXXXXX––––––
GMAC0–MCK1TZPM––––X––––––––––––X–XXX–––––––
GMAC1–MCK1TZPM––––X––––––––––––X–XXX–––––––
SDMMC0–MCK1TZPM––––X––––––––––––X–XXX–––––––
SDMMC1–MCK1TZPM––––X––––––––––––X–XXX–––––––
SDMMC2–MCK1TZPM––––X––––––––––––X–XXX–––––––
XDMAC2–MCK1XDMAC2––––X––––––––––––XXXXXX––––X–
MCAN0 – MCK1TZPM––––––––––––––––X––––––––––––
MCAN1–MCK1TZPM–––––––––––––––––X–––––––––––
MCAN2–MCK1TZPM––––––––––––––––X––––––––––––
MCAN3–MCK1TZPM–––––––––––––––––X–––––––––––
MCAN4–MCK1TZPM––––––––––––––––X––––––––––––
MCAN5–MCK1TZPM–––––––––––––––––X–––––––––––
ICM–MCK1TZPM–X––––––––––––––X––XXX–––––––
UDPHS0_DMA–MCK1TZPM–X––––––––––––––X––––––––––––
UDPHS1_DMA–MCK1TZPM–X–––––––––––––––X–––––––––––
OHCI_DMA – MCK1TZPM–X––––––––––––––X––––––––––––
EHCI_DMA–MCK1TZPM–X–––––––––––––––X–––––––––––
TZAESB–MCK1TZAESBASC–X–––––––––––––––––XXXX––––––
ISC–MCK3TZPM–––X–––––––––––––––––––––––––
Note:
  1. Refer to the following sections for details on each configuration method.
  2. “AS” stands for Always Secure; this configuration cannot be changed.