4.5.5.4 RSTC Generic Reset Register
| Name: | RSTC_GRSTR |
| Offset: | 0xE4 |
| Reset: | 0x00000070 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| USB_RST3 | USB_RST2 | USB_RST1 | DDR_PHY_RST | DDR_RST | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 1 | 1 | 0 | 0 |
Bits 4, 5, 6 – USB_RSTx USB Reset
| Value | Name | Description |
|---|---|---|
| 0 | POR_DISABLED | POR is disabled. |
| 1 | POR_ENABLED | POR is enabled. |
Bit 2 – DDR_PHY_RST DDR PHY Reset
| Value | Description |
|---|---|
| 0 |
DDR PHY reset is asserted. |
| 1 |
DDR PHY reset is de-asserted. |
Bit 0 – DDR_RST DDR Reset
| Value | Description |
|---|---|
| 0 |
DDR controller reset is asserted. |
| 1 |
DDR controller reset is de-asserted. |