12.10.17 PIR7

Peripheral Interrupt Request Register 7
Note:
  1. Available on 40-pin devices only.
  2. Available on 28/40-pin devices only.
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR7
Offset: 0x0093

Bit 76543210 
     OPA4CIFOPA3CIFOPA2CIFOPA1CIF 
Access R/W/HSR/W/HSR/W/HSR/W/HS 
Reset 0000 

Bit 3 – OPA4CIF  OPA4 Self-Calibration Complete Interrupt Flag(1)

ValueDescription
1 OPA4 Self-Calibration has completed (must be cleared in software)
0 OPA4 Self-Calibration event has not occurred

Bit 2 – OPA3CIF  OPA3 Self-Calibration Complete Interrupt Flag(2)

ValueDescription
1 OPA3 Self-Calibration has completed (must be cleared in software)
0 OPA3 Self-Calibration event has not occurred

Bit 1 – OPA2CIF  OPA2 Self-Calibration Complete Interrupt Flag(2)

ValueDescription
1 OPA2 Self-Calibration has completed (must be cleared in software)
0 OPA2 Self-Calibration event has not occurred

Bit 0 – OPA1CIF OPA1 Self-Calibration Complete Interrupt Flag

ValueDescription
1 OPA1 Self-Calibration has completed (must be cleared in software)
0 OPA1 Self-Calibration event has not occurred
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.