11.5.7 PLL Control A

Name:	PLLCTRLA
Offset:	0x10
Reset:	0x00
Property:	Configuration Change Protection

Bit 7 – RUNSTDBY Run Standby

This bit controls whether the Phase-Locked Loop (PLL) is always running or not.

Note:

The requesting peripheral must take the PLL start-up time and PLL source start-up time into account.
The oscillator signal will only be available if requested and will be available after two PLL cycles.

Value	Description
0	The PLL will only run if requested by a peripheral ⁽¹⁾
1	The PLL will always run in Active, Idle and Standby sleep modes ⁽²⁾

This bit controls the Phase-Locked Loop (PLL) clock source.


Value	Name	Description
`0`	OSCHF	High-frequency internal oscillator as PLL source
`1`	EXTCLK	External clock as PLL source

This bit field controls the multiplication factor for the Phased-Locked Loop (PLL).