2.1 General Description
The Microchip LAN8670/1/2 is a compact, low power, and cost-effective single-port 10BASE-T1S Ethernet PHY designed according to IEEE Std 802.3‑2022 Clause 147. The device provides 10 Mbit/s half‑duplex transmit and receive capability over a single balanced pair of conductors such as Unshielded Twisted Pair (UTP) cable. The LAN8670/1/2 is designed for use in applications requiring an extended temperature range (-40°C to +125°C ambient) and is optimized for AEC-Q100 automotive Grade 1 use cases. The device is also compliant to automotive and industrial EMC and EMI requirements. The single power supply and simple bus interface network simplifies its integration into small form factor applications.
The LAN8670/1/2 allows for the creation of half‑duplex multidrop network topologies. The multidrop mode supports up to at least 8 PHYs connected to a common mixing segment of up to at least 25m in length. The ability to connect multiple PHYs to a common mixing segment reduces weight and implementation costs by requiring fewer connectors, individual cables and switch ports.
Access to the physical medium is managed by CSMA/CD and optionally supplemented by Physical Layer Collision Avoidance (PLCA) as per IEEE Std 802.3-2022 Clause 148. In addition to the single transmit opportunity per bus cycle in this standard, the LAN8670/1/2 has the ability to be configured with up to 8 additional transmit opportunities in each bus cycle. As an alternative to PLCA, the Application Controlled Media Access (ACMA) pin can be used to implement time-division multiple access (TDMA) to the physical medium.
The LAN8670/1/2 interfaces with an Ethernet MAC via standard MII/RMII, or via the Single Clock Media Independent Interface (SC-MII) which is similar to the MII but with fewer pins. The unique capability to use PLCA with RMII is covered by Microchip intellectual property (U.S. Pat. 11,516,855) allowing PLCA functionality with legacy reduced pin-count RMII applications. An integrated serial management interface (SMI) provides rapid register access and configuration at up to 4 MHz.
Microchip’s LAN8670/1/2 EtherGREEN energy efficient technology provides low power 10BASE-T1S PHY operation along with an ultra-low power sleep mode with flexible wake options.
In addition, the LAN8670/1/2 can be used to implement high-precision clock synchronization. This enables implementation of the IEEE Std 802.1AS profile, among others, of IEEE Std 1588 for applications utilizing AVB or other Time Sensitive Networking (TSN) standards. This feature can be used to provide a Timing Synchronization Service Interface (TSSI) as specified in IEEE Std 802.3-2022 Clause 90 (as amended by IEEE 802.3de) as part of a TSN implementation.
Advanced PHY diagnostics are provided, which enable troubleshooting and monitoring capabilities such as cable defect detection of shorts or opens, a receiver Signal Quality Indicator (SQI), PLCA diagnostics, over-temperature, under-voltage detection, comprehensive status interrupt support, and various loopback and test modes.
The LAN8670/1/2 is designed to be used in ISO 26262 Functional Safety applications. It fulfills the functional safety requirements for ASIL B. A Functional Safety Package is available, including Safety Manual; Failure Modes, Effects, and Diagnostic Analysis (FMEDA); and Dependent Failure Analysis (DFA). Please contact Microchip support for additional information.
An internal block diagram of the LAN8670/1/2 is shown in the following figure.
