25.11 Register Summary - Timer2
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x038B | Reserved | |||||||||
| 0x038C | T2TMR | 7:0 | T2TMR[7:0] | |||||||
| 0x038D | T2PR | 7:0 | T2PR[7:0] | |||||||
| 0x038E | T2CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x038F | T2HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x0390 | T2CLKCON | 7:0 | CS[3:0] | |||||||
| 0x0391 | T2RST | 7:0 | RSEL[4:0] | |||||||
| 0x0392 | T4TMR | 7:0 | T4TMR[7:0] | |||||||
| 0x0393 | T4PR | 7:0 | T4PR[7:0] | |||||||
| 0x0394 | T4CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x0395 | T4HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x0396 | T4CLKCON | 7:0 | CS[3:0] | |||||||
| 0x0397 | T4RST | 7:0 | RSEL[4:0] | |||||||
| 0x0398 | T6TMR | 7:0 | T6TMR[7:0] | |||||||
| 0x0399 | T6PR | 7:0 | T6PR[7:0] | |||||||
| 0x039A | T6CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
| 0x039B | T6HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
| 0x039C | T6CLKCON | 7:0 | CS[3:0] | |||||||
| 0x039D | T6RST | 7:0 | RSEL[4:0] | |||||||