26.3.2.2.1 Clock Generation

The SCL clock is designed to have a 50/50 duty cycle, where T_OF is considered a part of T_LOW. T_HIGH will not start until a high state of SCL has been detected.The BAUD bit field in the TWIn.MBAUD register and the SCL frequency are related by the following formula:

$f_{SCL}=\frac{f_{CLK\mathrm{\_}PER}}{10+2\times BAUD+f_{CLK\mathrm{\_}PER}\times T_R}\mathrm{(1)}$

Equation 1 can be transformed to express BAUD:

$BAUD=\frac{f_{CLK\mathrm{\_}PER}}{2\times f_{SCL}}-(5+\frac{f_{CLK\mathrm{\_}PER}\times T_R}{2})\mathrm{(2)}$

To ensure operation within the specifications of the desired speed mode (Sm, Fm, Fm+), follow these steps:

1. Calculate a value for the BAUD bit field using equation 2
2. Calculate T_LOW using the BAUD value from step 1:

   $T_{LOW}=\frac{BAUD+5}{f_{CLK\mathrm{\_}PER}}-T_{OF}\mathrm{(3)}$

3. Check if your T_LOW from equation 3 is above the specified minimum of the desired mode (T_{LOW_Sm}= 4700 ns, T_{LOW_Fm}= 1300 ns, T_{LOW_Fm+}= 500 ns)
   • If the calculated T_LOW is above the limit, use the BAUD value from equation 2
   • If the limit is not met, calculate a new BAUD value using equation 4 below, where T_{LOW_mode} is either T_{LOW_Sm}, T_{LOW_Fm}, or T_{LOW_Fm+} from the mode specifications:

     $BAUD=f_{CLK\mathrm{\_}PER}\times (T_{LOW\mathrm{\_}mode}+T_{OF})-5\mathrm{(4)}$