28.2.3.1 Clocks

By default, the CCL is using the peripheral clock of the device (CLK_PER).

Alternatively, the CCL can be clocked by a peripheral input that is available on LUT n input line 2 (LUTn_IN[2]). This is configured by writing a ‘1’ to the Clock Source Selection (CLKSRC) bit in the LUT n Control A (CCL.LUTnCTRLA) register. The Sequential block and the even LUT in the LUT pair (SEQn.clk = LUT2n.clk) are clocked by the same clock. It is advised to disable the peripheral by writing a ‘0’ to the Enable (ENABLE) bit in the Control A (CCL.CTRLA) register before configuring the CLKSRC bit in CCL.LUTnCTRLA.

Alternatively, the input line 2 (IN[2]) of an LUT can be used to clock the LUT and the corresponding Sequential block. This is enabled by writing a ‘1’ to the CLKSRC bit in the CCL.LUTnCTRLA register.

The CCL must be disabled before changing the LUT clock source: Write a ‘0’ to the ENABLE bit in CCL.CTRLA.