28.4 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | RUNSTDBY | ENABLE | ||||||
| 0x01 | SEQCTRL0 | 7:0 | SEQSEL[3:0] | |||||||
0x02 ... 0x04 | Reserved | |||||||||
| 0x05 | LUT0CTRLA | 7:0 | EDGEDET | CLKSRC | FILTSEL[1:0] | OUTEN | ENABLE | |||
| 0x06 | LUT0CTRLB | 7:0 | INSEL1[3:0] | INSEL0[3:0] | ||||||
| 0x07 | LUT0CTRLC | 7:0 | INSEL2[3:0] | |||||||
| 0x08 | TRUTH0 | 7:0 | TRUTH[7:0] | |||||||
| 0x09 | LUT1CTRLA | 7:0 | EDGEDET | CLKSRC | FILTSEL[1:0] | OUTEN | ENABLE | |||
| 0x0A | LUT1CTRLB | 7:0 | INSEL1[3:0] | INSEL0[3:0] | ||||||
| 0x0B | LUT1CTRLC | 7:0 | INSEL2[3:0] | |||||||
| 0x0C | TRUTH1 | 7:0 | TRUTH[7:0] | |||||||