6.10.4.5 System Configuration 0
| Name: | SYSCFG0 |
| Offset: | 0x05 |
| Reset: | 0xC4 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCSRC[1:0] | TOUTDIS | RSTPINCFG[1:0] | EESAVE | ||||||
| Access | R | R | R | R | R | R | |||
| Reset | 1 | 1 | 1 | 0 | 1 | 0 | |||
Bits 7:6 – CRCSRC[1:0] CRC Source
| Value | Name | Description |
|---|---|---|
| 0x0 | FLASH | CRC of full Flash (boot, application code and application data) |
| 0x1 | BOOT | CRC of the boot section |
| 0x2 | BOOTAPP | CRC of application code and boot sections |
| 0x3 | NOCRC | No CRC |
Bit 4 – TOUTDIS Time-Out Disable
When the TOUTDIS bit in FUSE.SYSCFG0 is ‘0’ and
the RSTPINCFG bit field in FUSE.SYSCFG0 is configured to GPIO or RESET, there
will be a time-out period after POR that blocks NVM writes.
The NVM write block will last for 768 OSC32K cycles after POR. The EEBUSY and
FBUSY bits in the NVMCTRL.STATUS register must read ‘0’ before
the page buffer can be filled or NVM commands can be
issued.
| Value | Description |
|---|---|
| 0 | NVM write block is enabled |
| 1 | NVM write block is disabled |
Bits 3:2 – RSTPINCFG[1:0] Reset Pin Configuration
Note: When
configuring the RESET pin as GPIO, there is a potential conflict between the
GPIO actively driving the output, and a high-voltage UPDI enable sequence
initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K
cycles after a System Reset. Enable any interrupts for this pin only after this
period.
| Value | Description |
|---|---|
| 0x0 | GPIO |
| 0x1 | UPDI |
| 0x2 | RESET |
| Other | Reserved |
Bit 0 – EESAVE EEPROM Save During Chip Erase
Note: If the device is locked, the
EEPROM is always erased by a chip erase, regardless of this bit.
| Value | Description |
|---|---|
| 0 | EEPROM erased during chip erase |
| 1 | EEPROM not erased under chip erase |