24.5.2 Receiver Data Register High Byte
Reading the USARTn.RXDATAH register location will return the contents of the ninth RXDATA bit plus Status bits.
The receive buffer consists of a two-level buffer. The data buffer and the corresponding flags in the high byte of USARTn.RXDATAH will change state whenever the receive buffer is accessed (read). If the CHSIZE bits in the USARTn.CTRLC register are set to 9BIT Low byte first, read the USARTn.RXDATAL register before the USARTn.RXDATAH register. Otherwise, always read the USARTn.RXDATAH register before the USARTn.RXDATAL register in order to get the correct flags.
| Name: | RXDATAH |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXCIF | BUFOVF | FERR | PERR | DATA[8] | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and
cleared when the receive buffer is empty (that is, does not contain any unread
data). When the receiver is disabled the receive buffer will be flushed and,
consequently, the RXCIF bit will become ‘0’.
Bit 6 – BUFOVF Buffer Overflow
The BUFOVF flag indicates data loss due to a “receiver buffer full” condition. This flag is set if a Buffer Overflow condition is detected. A buffer overflow occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift register, and a new Start bit is detected. This flag is valid until the receive buffer (USARTn.RXDATAL) is read.
This flag is not used in Master SPI mode of operation.
Bit 2 – FERR Frame Error
The FERR flag indicates the state of the first Stop bit of the next
readable frame stored in the receive buffer. This bit is set if the received
character had a frame error, that is, when the first Stop bit was
‘0’ and cleared when the Stop bit of the received data is
‘1’. This bit is valid until the receive buffer
(USARTn.RXDATAL) is read. The FERR bit is not affected by the SBMODE bit in the
USARTn.CTRLC register since the receiver ignores all, except for the first Stop
bit.
This flag is not used in Master SPI mode of operation.
Bit 1 – PERR Parity Error
If parity checking is enabled and the next character in the receive
buffer has a parity error, this flag is set. If parity check is not enabled the
PERR bit will always be read as ‘0’. This bit is valid until
the receive buffer (USARTn.RXDATAL) is read. For details on parity calculation
refer to 24.3.4.1 Parity. If USART is set to LINAUTO mode, this bit will
be a parity check of the protected identifier field and will be valid when the
DATA[8] bit in the USARTn.RXDATAH register reads low.
This flag is not used in Master SPI mode of operation.
Bit 0 – DATA[8] Receiver Data Register
When the USART receiver is configured to LINAUTO mode, this bit
indicates if the received data are within the response space of a LIN frame. If
the received data are in the protected identifier field, this bit will be read
as ‘0’. Otherwise, the bit will be read as
‘1’. For a receiver mode other than LINAUTO mode, the DATA[8]
bit holds the ninth data bit in the received character when operating with
serial frames with nine data bits.