1.2 Sequencing Requirements

Power sequencing refers to the controlled application and disconnection of voltage to the power rails of a system, following a specific order and defined time intervals during both power-up and power-down events. This sequence is typically managed by the order in which the Power Management Integrated Circuit (PMIC) enables or disables the system's rails.

Sequencing requirements can vary depending on the specific FPGA in use. While many modern FPGAs indicate that strict sequencing is not mandatory, relying solely on this guidance may not yield the most robust power solution. During system start-up and shutdown, it is essential to prevent unintended power application, which could result in power spikes, bus contention, or potentially damaging latch-up conditions. Implementing a controlled and predetermined power-up and power-down sequence helps mitigate these risks and ensures reliable system operation.

A commonly recommended start-up sequence is to power the core logic voltage first, followed by the input/output voltage, and then any peripheral devices. However, this “inside-out” approach may not always apply, as factors such as the configuration of the ESD network can influence the optimal sequence. Therefore, it is important to consult the documentation for each specific product to determine the recommended sequencing requirements. The overall system start-up sequence should then be developed by integrating these individual requirements.

It is also important to consider scenarios where residual power remains in system bypass and filter capacitors at start-up, such as after a brief power interruption (brown-out) or when the system is not fully discharged before power is reapplied. In these cases, proper shutdown sequencing is necessary to ensure an orderly power-down, prevent potential damage, and leave the system in a safe state for subsequent start-up.