35.8.7.4 Baud Rate

Table 35-67. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	BAUD
Offset:	0x0C
Reset:	0x0000
Property:	PAC Write-Protection, Enable-Protected


Bit	31	30	29	28	27	26	25	24
	HSBAUDLOW[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	HSBAUD[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BAUDLOW[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BAUD[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – HSBAUDLOW[7:0] High Speed Host Baud Rate Low

HSBAUDLOW non-zero: HSBAUDLOW indicates the SCL low time in High-speed mode according to

$HSBAUDLOW = f_{GCLK} \cdot T_{LOW} - 1$

HSBAUDLOW equal to zero: The HSBAUD register is used to time T_LOW,T_HIGH,T_SU;STO, T_HD;STAand T_SU;STA.. T_BUFis timed by the BAUD register.

Bits 23:16 – HSBAUD[7:0] High Speed Host Baud Rate

This bit field indicates the SCL high time in High-speed mode according to the following formula. When HSBAUDLOW is zero, T_LOW,T_HIGH,T_SU;STO,T_HD;STAand T_SU;STAare derived using this formula. T_BUF is timed by the BAUD register.

$HSBAUD = f_{GCLK} \cdot T_{HIGH} - 1$

Bits 15:8 – BAUDLOW[7:0] Host Baud Rate Low

If this bit field is non-zero, the SCL low time will be described by the value written.

For more information on how to calculate the frequency, see Clock Generation - Baud-Rate Generator.

Bits 7:0 – BAUD[7:0] Host Baud Rate

This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL.