53 Revision History

Note: The data sheet revision is independent of the die revision (Revision bit in the Device Identification register of the Device Service Unit, DSU.DID.REVISION) and the device variant (last letter of the ordering number).

Revision K - 05/2025

The following updates were performed for this revision:


Section	Updates
Up to 8 MB Flash, 1 MB SRAM, Hardware Security Module, Secure Boot, Floating Point Unit (FPU,) Advanced Analog, Gigabit Ethernet, HS USB, CANFD, and Peripheral Touch Controller (PTC)	Updated Operating Conditions
Ordering Information	Updated the diagram to include new temperature range
Hardware Security Module (HSM)	Added a new section, Performance
Non-Volatile Memory Controller (NVMCTRL)	Added CTRLB register
Gigabit Ethernet Media Access Controller (GMAC / ETH)	Updated Signal Interface with all new content for Table 32-1 Added a new section, Clocks
Electrical Characteristics	Updated the following sections with new min, typ, or max specifications: Power Supply MCU Active Power MCU Idle Power MCU Standby Power

Revision J - 12/2024

The following updates were performed for this revision:


Section	Updates
General	Updated Product naming throughout the document
Configuration Summary	Updated Table 1-1 and Table 1-2 with new part numbers for the CA9x and CA8x part designations
Guidelines for Getting Started	Updated Definitions of Terms Used to remove circular references
Ordering Information	Updated the diagram to include new memory sizes and Family variants
Pinout	Added new Part numbers to the following packages: 100-pin TQFP EP 144-pin TQFP EP 144-pin TFBGA
Signal Descriptions	Updated Table 6-7 SERCOM0 Through SERCOM9 Pinout I/O Descriptions (Peripheral Function D) with new descriptions for each pin name
Product Mapping	Updated the following sections with a new column in each table for 1 MB Flash and 0.5 MB RAM: Code Address Space SRAM Address Space Peripheral Address Space External RAM Address Space
Memories	Added a new section, Fuse Area Selection Updated the following sections: FUCFUG2 FUCFUG3 FUCFUG4 FUCFUG9
Tightly Coupled Memory with ECC (TCM)	Clarified a note in the CTRLA register
Main Clock (MCLK)	Updated the bitfield description tables in the following registers, to reflect a change from Interrupt to Peripheral Clock: CLKMSK0 CLKMSK1 CLKMSK2
Direct Memory Access Controller (DMAC)	Updated text for the NULL Pointer in Linked List Updated the CHCTRLAk Register with a new description value for the LLEN bit Renamed the WRELL bitfield to LL in the CHINTFk Registe
Power Manager (PM)	Updated the description for the RAMCFG bit in the STDBYCFG Register
Gigabit Ethernet Media Access Controller (GMAC / ETH)	Clarified mbps support in PHY Interface
Event System (EVSYS)	Removed all references to erroneous Synchronous operation throughout the chapter Updated the Event Generator (EVGEN) Mapping table with new values for the value column in the CHANNELn Register Updated the Path Type column of the Event User Mapping table in the USERm Register
SERCOM USART	Clarified verbiage for the TX buffer and shift register in SERCOM USART Data Transmission Added a note for the use of the Data Register Empty Flag to SERCOM USART LIN Host Updated the CTRLC Register with clarified text for notes in the HDRDLY and BRKLEN bitfields
Hi-Speed Universal Serial Bus (USB)	Added a note to the following registers regarding CAL OTP: PHY00 PHY04 PHY08 PHY0C PHY10 PHY14 PHY18 PHY1C PHY20 PHY24 PHY28 PHY44 PHY48 PHY4C PHY50
External Bus Interface (EBI)	Removed erroneous mention of DRAM in Features Updated the Block Diagram to reflect new SRAM Controller naming
Analog-to-Digital Converter (ADC)	Updated bitfield reset properties for the TRGSRC bitfield in the following registers: CONFIG[0].CHNCFG4 CONFIG[0].CHNCFG5 CONFIG[1].CHNCFG4 CONFIG[2].CHNCFG4 CONFIG[3].CHNCFG4
Analog Comparators (AC)	Added a note to Inputs Swapping
Timer/Counter for Control Applications (TCC)	Removed obsolete information from Counter Operation Added a note to Capture Operations Updated signal naming in the diagram for the Circular Buffer
Package Drawings	Added a note on where to find the most current packages
Schematic Checklist	Added information for referencing supporting documentation

Revision H - 09/2024

The following updates were performed for this revision:


Section	Updates
Up to 8 MB Flash, 1 MB SRAM, Hardware Security Module, Secure Boot, Floating Point Unit (FPU,) Advanced Analog, Gigabit Ethernet, HS USB, CANFD, and Peripheral Touch Controller (PTC)	Updated the Table 1. "Packages" to reflect the addition of 144-Ball and 176-Lead Packages
Configuration Summary	Updated both tables to reflect the addition of 144-Ball and 176-Lead packages
Ordering Information	Added the information for the 144-Ball and 176-Lead packages
Pinout	Added in the following packages: 144-pin 176-pin
Signal Description	Added 144-Ball and 176-Lead information to all tables in this section
Electrical Characteristics	Updated CPU Electrical Characteristics with 144-Ball and 176-Lead information Updated SPI Electrical Specifications with new tables for SPI Host Mode, and SPI Client Mode
Package Drawings	Added in the following packages: 144-Ball TFBGA 176-Lead TFBGA

Revision G - 04/2024


Section	Updates
General	Updated instances of PIC32CZ CA90 to PIC332CZ CA9x to reflect a new variant, the PIC32CZ CA91
Configuration Summary	Added a new information for a new variant of PIC32CZ CA9x, the PIC32CZ CA91
Ordering Information	Added new package specification for the PIC32CZ CA91
DSU	Added a note and updated information in the DID Register
Electrical Characteristics	Updated the Ambient Temperature under bias in Absolute Maximum Electrical Characteristics Updated the Max CPU Frequency for table 48.3 and the typ specification for table 48.5 in CPU Electrical Characteristics Updated Parameter numbering for REG_49 in Power Supply Removed obsolete FCLK_27 data from Maximum Clock Frequencies Updated data for MSP_1 in Table 48-30, and SSP_1 in table 48-31 of Serial Peripheral Interface (SPI) Electrical Specifications

Revision F - 08/2023


Section	Updates
Features	Updated Analog Peripherals to display the proper number of external and internal inputs
Guidelines for Getting Started	Updated the packages for Hypothetical Application Example Updated the wattage, and temperatures specifications for the Calculations and Rule Cross check sections of Safe Power Operating Condition Check of the Previous Example
Pinout	Updated pin B3 in the 208-pin package pinout
Memories	Updated the following Memory sections with new offsets: FSEQ0 AFSEQ0 FUCFG0 FUCFG1 FUCFG2 FUCFG5 FUCFG6 FUCFG7 FUCFG8 FUCFG9 FUCFG10-31
DSU	Updated the revision Id for the REVISION bitfield in the DID Register Updated the registerDID by adding a table
PM	Replaced older chapter with a new updated version
ETH	Added a note to the ADDR bitfield in the following registers: SABx SATx
EVSYS	Updated the USERm register to properly display as an 8-bit register
USB	Removed erroneous text from the bitfields in the LPMINTR Register
ADC	Restructured the Registers to display by offset order Updated the Block Diagram Updated the offsets for the following registers: CONFIG[n].CORCTRL CMPCTRL[n] CTLINTENCLR CTLINTENSET INTENCLR[n]
Electrical Characteristics	Updated XR7 to X7R and updated the notes in Power Supply Updated the notes to the tables in Analog-to-Digital Converter (ADC) Electrical Specifications
Schematic Checklist	Introduction - Updated Note 4 and added a new Note 8

Revision E - 05/2023

Numerous typographical updates were done throughout this document, along with the updates listed as follows:


Section	Updates
General	Removed any references to packages that were not 208-pin throughout the document
Features	Updated Operating Conditions Updated the Software Tools and Support section with all new information
Product Mapping	Reformatted table headers
OSC32KCTRL	Removed erroneous content pertaining to Gain Boost from 32kHz External Crystal Oscillator (XOSC32K) Operation
MCLK	Updated the note for the MSKn bitfield in the CLKMSK0 Register along with minor clarifications in the associated tables
RTC	Updated the RTC Block Diagram (Mode2 - Clock/Calendar) Updated the equation in Initialization Updated the description for the PRESCALER Bitfield in the CTRLA Register in Clock/Calendar mode Added a note to the FREQCORR Register containing an equation
SUPC	Updated the Temperature Calibration Summary with new references to an MPLAB Harmony v3 example
EIC	Updated the CONFIG Register to display the proper values for CONFIG0 and CONFIG1
NVMCTRL	Clarified verbiage in Flash Retention and Endurance Clarified verbiage in Pre-Program Added a note to Single Write Sequence Removed and erroneous reference in Program Erase Timing and added a note
ETH	Added the following new registers: WPCTRL EFIEN AXIMP RSCCTRL INTMOD SYSWT DMAAM PTPRXUC PTPTXUC DPRAMFD AFP TSSSH TPQ1 TPQ2 TPQ3 Renamed the following register: TSSSL
PORT	Removed an erroneous table from the PINCFGn Register
SERCOM	Added all new content to the following sections: Overview Features Clock Generation - Baud Rate Generator
SERCOM USART	Replaced Chapter with all new content
SERCOM I²C	Updated the FILTSEL bitfield table values for the following registers: CTRLA - Client CTRLA - Host
USB	Added a note to Configuration Added a new PHY Register section
EBI	Added a note to Features
ADC	Updated the naming convention and offset equation for the CONFIGn.CORTCTRL Register Updated the bitfield display for the CONFIG[0].CHNCFG5 Register
TCC	Added notes to the following registers: PATTBUF PERBUF CCBUFy
I²S	Updated the table for the FRMCNT bitfield for the FRAMECTRL Register

Revision D - 02/2023

Numerous typographical updates were done throughout this document, along with the updates listed as follows:


Section	Updates
General	Updated DPLL to read PLL throughout the entire document
Features	Updated Analog Peripherals with new conversion rate information
Pinout	Updated the following Pinouts with bolding for 5.5V tolerant pins: 100-Pin TQFP, 144-BallTQFP, 144-BallTFBGA, 176-LeadTFBGA, 208-pin TFBGA
Power Supplies and Startup Considerations	Updated signal names in Power Supplies
Product Mapping	Removed ITCM data from Code Address Space Added ITCM data to SRAM Address Space
Memories	Updated the Physical Memory Map with a new start address for Embedded Flash
PAC	Removed deprecated bitfields from the following registers: INTFLAGAHB INTFLAGB STATUSB
Clock Distribution System	Updated Figure 17-2 in Clock Distribution by removing incorrect naming from the DFLL48M
OSCCTRL	Removed erroneous RC48M information from Features Removed erroneous RC48M information from PLL Basic Operation Added a new note to Clock Failure Detection Operation Added new notes to the STARTUP Bitfield in the XOSCCTRLA Register
GCLK	Minor updates removing CLK from the Block Diagram Removed an erroneous note and updated pin names in External Clock Added an important note to Synchronization Updated reset values for the GENCTRLn Register and removed incorrect RC48M labeling from Generator Clock Source Selection table in the SRC Bitfield Added new notes to the PCHCTRL (Index) GCLK Mapping table in the GEN bitfield of the PCHCTRLm Register
MCLK	Updated the CLKDIVn Register with a new Important note, and a new reset value Marked as Reserved the MSK12 bit in the CLKMSK0 Register Updated the Interrupts in the table for the MSKn bitfield in the CLKMSK2 Register
RTC	Added an Important note to Active Layer Protection Added an Important note to the CTRLA Register in COUNT32 mode Added an Important note to the TAMPID Register Added an Important note to the CTRLA Register in COUNT16 mode Added an Important note to the CTRLA Register in Clock/Calendar mode
SUPC	Added a note to the LVD Register Added a new section for Temperature Calibration
PM	Added an Important note to Sleep Modes
NVMCTRL	Removed deprecated CTRLB Register
EVSYS	Updated the PATH bitfield with a new note in the CHANNELn Register
PORT	Added note 4 to the SLEWLIM bitfield in the PINCFGn Register
SERCOM	Added notes 3, and 4 to the Peripheral Dependencies table
USB	Added minor clarification for Host Mode only to Overview and Features Added verbiage for VUSB3V3_0 and VUSB3V3_1 to the Signal Description Added new PHY Registers to the following Register Banks: USB Common Registers Device Mode Endpoint1-7 Registers
ADC	Clarified 12 bit resolution support in the Overview and Features Updated CTRLB to CTRLD in the Block Diagram and the ADC Trigger Block Diagram Added a new Important note to Conversion Timing and Sampling Rate Added Trigger Rule 4 to Trigger Limitations Added Notes 7 and 8 to Interleaving Samples for Higher Sample Rate Added a note to the CNT bitfield of the CTRLC Register Added a note to the STRGSRC bitfield of the CONFIG[0].CORCTRL Register Added notes 4 and 5 to the WKUPCLKCNT bitfield of the CTRLD Register Added notes 3 and 4 to the ADCDIV Bitfield of the CONFIG[0].CORCTRL Register
AC	Clarified COMPCTRLn.SPEED for high speed in Comparator Configuration
TCC	Added an Important note to DMA Operation
I²S	Clarified modes for audio data in Audio Protocol Overview Updated Control Register information in SPI Operation Updated Register naming in Ignore Receive Overflow Updated Register naming in Receive Overflow Interrupt Enable
Electrical Characteristics	Added note 9 for the table in Power Supply Updated note 6 with new verbiage for table in DFLL/FPLL Electrical Specifications
Schematic Checklist	Added new sections to the Introduction detailing proper product usage

Revision C - 12/2022

Numerous typographical updates were done throughout this document, along with the updates listed as follows:


Section	Updates
General	Removed erroneous references to On-the-Go (OTG) for the USB throughout the document
Features	Removed erroneous references to On-the-Go (OTG)
OSCCTRL	Removed an erroneous section, DFLL48M USB Clock Recovery Mode from Additional DFLL48M Features Updated the note for the DFLLCTRLB Register and removed the USBCRM bitfield, which was erroneously included in the last revision
DMAC	Removed erroneous text from the BYTORD bitfield in the CHCTRLBk Register
SQI	Removed erroneous content from the SWRST bitfield in the CTRLA Register Removed erroneous content from the SQI bitfield in the INTFLAG Register
USB	Removed erroneous references to On-The-Go (OTG) throughout the Chapter
EBI	Corrected a minor typographical error in the bitfield NEW CYCLE in the CYCLE Register
SDHC	Removed erroneous text referring to card detection from the INTCLKEN bitfield in the CCR Register
ADC	Added new content to the table for the COREINTERLEAVED bitfield in the CTRLC Register
Electrical Characteristics	Updated Absolute Maximum Electrical Characteristics with new current information Updated the Typ and Max specifications in MCU Active Power Replaced the existing tables with updated tables in the following sections: MCU Idle Power I/O Pin Electrical Specifications External Oscillator (XOSC) Electrical Specifications External 32.768 kHz Oscillator (XOSC32) Electrical Specifications Table 48-20 in DFLL/FPLL Electrical Specifications Table 48-24 in Analog-to-Digital Converter (ADC) Electrical Specifications Serial Peripheral Interface (SPI) Electrical Specifications UART Electrical Specifications I²S Electrical Specifications I²C Electrical Specifications SQI/QSPI Electrical Specifications Controller Area Network (CAN) Electrical Specifications
Packaging Information	Updated the following Package drawings: 100 Lead TQFP-EP and 144 pin TQFP-EP

Revision B - 08/2022

Numerous typographical updates were done throughout this document, along with the updates listed as follows:


Section	Updates
General	Updated terminology of RESET_N, Reset_n, RESET_, and RESET_n to read RESET Updated every register in the document with the addition of a register legend
Features	Removed erroneous references to VDDIO and VDDREG Removed the “Audio Interfaces” section
Pinout	Added new tables for all packages
Signal Description	Updated PORT to read Peripheral in all Table Titles Removed Tables for Gigabit Media Access Controller MII and RMII
Power Supplies and Startup Considerations	Removed obsolete Power Supply Pins table from Chapter heading Changed colors in the Power Domain Overview Block Diagram so they were using the same shade of purple Spelled out signal names in Power-On Reset and Brown-Out Detectors
Product Mapping	Updated table formatting with minor changes to display information more clearly, removed 512 MB references
Processor and Architecture	Updated the NVIC Interrupt Line Mapping table with new signal names for the I²S, removing SPI references
Memories	Added Features listing to Embedded Memories Added new Memory Mapping for FUCFG0, FUCFG1, FUCFG2, , , FUCFG5, FUCFG3, FUCFG4, FUCFG6 and FUCFG7. Reformatted FUCFG9
MCRAMC	Updated the Peripheral Dependencies table Rewrote portions of ECC SECDED - ECC Functionality
TCM	Rewrote Overview to include feature set Updated the block diagram with proper Module naming Updated the Peripheral Dependencies table Removed Disabling/Enabling the Module During Runtime Updated the Register Reset value in CTRLA, and reformatted the ENABLE and SWRST bitfields Reformatted the FLTMD and FLTEN bitfields in the FLTCTRL Register Reformatted the ITCMMASTER Bitfield of the IFLTCAP Register Reformatted the ERR2, and ERR1 Bitfields in the IFLTSYN Register Reformatted the D1D0EN Bitfield in the DFLTADR Register Reformatted the ERR2, and ERR1 Bitfields in the DFLTSYNn Register
PAC	Updated the Peripheral Dependencies table Added a note to the INTFLAGAHB Register Added a note and new bitfield properties to the INTFLAGA Register Added a note and new bitfield properties to the INTFLAGB Register Removed erroneous bitfields for MBIST and NVMWFT from INTFLAGC Updated the Register Offset for STATUSA and added a note Added a note to STATUSB Removed erroneous bitfields for MBIST and NVMWFT from STATUSC
DSU	Removed erroneous information on Device Configuration Fuses from Features Updated the Peripheral Dependencies table
Clock Distribution System	Added a new Block Diagram
OSCCTRL	Updated signal naming in the Block Diagram Updated the Peripheral Dependencies table Updated signal naming in Clocks, Principles of Operation, and External Multipurpose Crystal Oscillator (XOSC) Operation Reformatted the bitfields in the INTENCLR, INTENSET, and STATUS Registers
OSC32KCTRL	Updated the Peripheral Dependencies table Updated the table for the CGM bitfield in the XOSC32K Register, and removed the BOOST bitfield
GCLK	Reformatted the Block Diagram Updated the Peripheral Dependencies table
MCLK	Updated Signal names in the Block Diagrams Updated the Peripheral Dependencies table Reformatted the CLKMSK0, CLKMSK1, and CLKMSK2 Registers
WDT	Updated the Peripheral Dependencies table Updated the bitfield properties for all bits in the CTRLA Register Reformatted the CONFIG Register Reformatted the EWCTRL Register
FREQM	Updated the Peripheral Dependencies table
RTC	Updated signal names, Inputs, and Outputs in the RTC Block Diagrams Added a new note to the Signal Description table, and new inputs and outputs Updated the Peripheral Dependencies table Added a note to the EVCTRL, INTENCLR, INTENSET, INTFLAG, TAMPCTRL, TAMPID, and TAMPCTRLB 32-bit Counter Mode Registers Added a note to the EVCTRL, INTENCLR, INTENSET, and INTFLAG 16-bit Counter Mode Registers
DMAC	Updated the Peripheral Dependencies table
SUPC	Removed the note from the Peripheral Dependencies Table Reformatted the bitfields in the BOR Register Reformatted the TGLOMn bitfield and added a note to the BKOUT Register Renamed the bitfields in the BKIN Register
PM	Reformatted the IORET Bitfield in the CTRLA Register Reformatted the SLEEPRDY Bitfield in the INTFLAG Register Reformatted the STDBYCFG, and HIBCFG Registers
RSTC	Updated the Peripheral Dependencies table Updated Signal naming in Reset Causes and Effects Updated the Reset for the BKUPEXIT Register
EIC	Updated EXTINT to read EIC_EXTINTX in the entire chapter Removed the second part of the Block Diagram Updated the Signal naming in the Signal Description Added a new Peripheral Dependencies Table Rewrote Interrupts Rewrote Initialization Updated Register and Signal naming in External Pin Processing Removed NMI Content from the chapter, removed the NMICTRL and NMIFLAG Registers Reformatted bitfields, Properties and resets in the following registers: CTRLA EVCTRL INTENCLR INTENSET INTFLAG ASYNCH CONFIG DEBOUNCEN DPRESCALER PINSTATE
MLB	Updated the Peripheral Dependencies table
NVMCTRL	Updated Signal naming in the Block Diagram
Flash Controller, Write	Removed the Note from Peripheral Dependencies
Flash Controller, Read	Updated the Peripheral Dependencies table
GMAC	Updated the Peripheral Dependencies table
PORT	Updated the Peripheral Dependencies table Updated the Overview of the Port with new resistor info in the Functional Description Added an Important note to Principle of Operation Added a note to the Pin Configurations Summary table in I/O Pin Configurations Reformatted the WRCONFIG Register Reformatted the PMUXm Register Reformatted the PINCFGn Register
SERCOM	Updated the Peripheral Dependencies table
SERCOM I²C	Added a note to the CTRLA Client Register
HSUSB	Updated signal names in the Signal Description table Updated the Peripheral Dependencies table
CAN	Updated the Peripheral Dependencies table
EBI	Removed the note from Peripheral Dependencies
ADC	Updated the Peripheral Dependencies table Reformatted and updated the following registers with tables and proper display: CORCTRLn CHNCFG10 CHNCFG11 CHNCFG12 CHNCFG13 CHNCFG20 CHNCFG21 CHNCFG22 CHNCFG23 CHNCFG30 CHNCFG31 CHNCFG32 CHNCFG33 CHNCFG40 CHNCFG41 CHNCFG42 CHNCFG43 CHNCFG50 FLTCTRLn Updated the naming for the following Registers: CALCTRLn EVCTRLn CMPCTRLn PFFDATA PFFCTRL INTENCLRn INTENSETn INTFLAGn Removed the DBGCTRL Register
AC	Added a Important note to Overview Updated the Block Diagram with a new image Updated the Peripheral Dependencies table Updated terminology in the entire chapter, changing COMPCTRLx to COMPCTRLn Renamed or reformatted the following registers: CTRLA CTRLB CTRLC EVCTRL INTENCLR INTENSET INTFLAG STATUSA STATUSB DBGCTRL SYNCBUSY COMPCTRLn DACCTRLn WINCTRL
TCC	Updated the Peripheral Dependencies table Updated the DMAOS Bitfield with a new table in the CTRLA Register
Electrical Characteristics	Removed the note and DC_7 information form the Operating Frequency versus Voltage table Removed Extended Temperature Range information, and updated the equations for Power Dissipation in the CPU Thermal Operating Conditions table Updated BOD33 to read BORVDDx througout the chapter Updated terminology in the Comparator Electrical Specifications changing COMPCTRLx to COMPCTRLn
Packaging	The following new packages were added: 100-pin TQFP-EP 144-pin TQFP-EP
Schematic Checklist	Replaced the Diagram in the Introduction

Revision A - 12/2021

This is the initial release of this document.

PIC32CZ CA80/CA90 Family

53 Revision History

Revision K - 05/2025

Revision J - 12/2024

Revision H - 09/2024

Revision G - 04/2024

Revision F - 08/2023

Revision E - 05/2023

Revision D - 02/2023

Revision C - 12/2022

Revision B - 08/2022

Revision A - 12/2021