PIC32CZ CA80/CA90 Family

21.6.5 Peripheral BUS Clock Enable Mask0 Register

Note: AHB = Advanced High-Performance Bus

APB = Advanced Peripheral Bus

AXI = Advanced eXtensible Interface

Table 21-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CLKMSK0
Offset:	0x3C
Reset:	0xFFFFFFFF
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	MSK31	MSK30	MSK29	MSK28	MSK27	MSK26	MSK25	MSK24
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
	MSK23	MSK22	MSK21	MSK20	MSK19	MSK18	MSK17	MSK16
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8
	MSK15	MSK14	MSK13			MSK10	MSK9	MSK8
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	1	1	1			1	1	1


Bit	7	6	5	4	3	2	1	0
	MSK7	MSK6	MSK5	MSK4	MSK3	MSK2	MSK1	MSK0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1

Bits 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – MSKn Clock Enable Mask


Bit Number	Description
0	DSU
1	DSU
2	FCW
3	FCW
4	FCR
5	FCR
6	PM
7	SUPC
8	RSTC
9	OSCCTRL
10	OSC32KCTRL
11	(RESERVED ALWAYS = 1)
12	(RESERVED ALWAYS = 1)
13	FREQM
14	WDT
15	RTC
16	EIC
17	PAC
18	PAC
19	DRMTCM
20	MCRAMC
21	TRAM
22	PORT
23	PORT
24	DMAC
25	DMAC
26	Bus Matrix
27	Bus Matrix
28	Boot ROM
29	Boot ROM
30	EVSYS
31	SERCOM0

Value	Description
0	Peripheral Clock is disabled.
1	Peripheral Clock is enabled.

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 – MSKn Clock Enable Mask

Note: MSK11 and MSK12 are reserved and must be set to 1.

Value	Description
0	Clock is disabled.
1	Clock is enabled.

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