18.7.2 Interrupt Enable Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PLL1LOCKR | PLL0LOCKR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLFAIL | DFLLRCS | DFLLUNF | DFLLOVF | DFLLLOCK | DFLLRDY | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKFAIL | XOSCFAIL | XOSCRDY | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bits 24, 26 – PLLnLOCKR PLL Lock Rise Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the PLL Lock Rise Interrupt Enable bit, which disables the PLL Lock Rise interrupt.
| Value | Description |
|---|---|
| 0 | The PLL Lock Rise interrupt is disabled. |
| 1 | The PLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the PLL Lock Rise Interrupt flag is set. |
Bit 13 – DFLLFAIL DFLL Startup Failure Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Startup Failure Interrupt Enable bit, which disables the DFLL Startup Failure interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL48M Startup Failure interrupt is disabled. |
| 1 | The DFLL48M Startup Failure interrupt is enabled, and an interrupt request will be generated when the DFLL Startup Failure Interrupt flag is set. |
Bit 12 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL48M Reference Clock Stopped interrupt is disabled. |
| 1 | The DFLL48M Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set. |
Bit 11 – DFLLUNF DFLL Tuner Underflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Tuner Underflow Interrupt Enable bit, which disables the DFLL Tuner Underflow interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Tuner Underflow interrupt is disabled. |
| 1 | The DFLL Tuner Underflow interrupt is enabled, and an interrupt request will be generated when the DFLL Tuner Underflow Interrupt flag is set. |
Bit 10 – DFLLOVF DFLL Tuner Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Tuner Overflow Interrupt Enable bit, which disables the DFLL Tuner Overflow interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Tuner Overflow interrupt is disabled. |
| 1 | The DFLL Tuner Overflow interrupt is enabled, and an interrupt request will be generated when the DFLL Tuner Overflow Interrupt flag is set. |
Bit 9 – DFLLLOCK DFLL Lock Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Lock Interrupt Enable bit, which disables the DFLL Lock interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Lock interrupt is disabled. |
| 1 | The DFLL Lock interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Interrupt flag is set. |
Bit 8 – DFLLRDY DFLL Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Ready interrupt is disabled. |
| 1 | The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set. |
Bit 2 – CLKFAIL XOSC Clock Failure Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC Clock Failure interrupt is disabled. |
| 1 | The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated when the XOSC Clock Failure Interrupt flag is set. |
Bit 1 – XOSCFAIL XOSC Startup Failure Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the XOSC Startup Failure Interrupt Enable bit, which disables the XOSC Startup Failure interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC Startup Failure interrupt is disabled. |
| 1 | The XOSC Startup Failure interrupt is enabled, and an interrupt request will be generated when the XOSC Startup Failure Interrupt flag is set. |
Bit 0 – XOSCRDY XOSC Ready Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC Ready interrupt is disabled. |
| 1 | The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. |