47.6.5 SPI Control Audio Register

Table 47-8. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: AUDCTRL
Offset: 0x10
Reset: 0x00
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       AUDWDMODE[1:0] 
Access R/WR/W 
Reset 00 
Bit 76543210 
  AUDFMT[2:0]AUDMONO AUDMOD[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 9:8 – AUDWDMODE[1:0] Serial Word Length bits (Ignored when AUDEN=0)

For AUDEN = 1: & AUDFMT= 3’b000
COMMUNICATION
1124-bit Data, 32-bit Channel/1/32-bit Frame pulse
1032-bit Data, 32-bit Channel/1/32-bit Frame pulse
0116-bit Data, 32-bit Channel/1/16/32-bit Frame pulse
0016-bit Data, 16-bit Channel/1/16-bit Frame pulse
For AUDEN = 1: & AUDFMT= 3’b001
COMMUNICATION
11Reserved
10I2S -24-bit raw audio data (slot), 32-Bit Ch/1/32-bit Frame pulse
01I2S -20-bit raw audio data (slot), 32-Bit Ch/1/32-bit Frame pulse
00I2S -16-bit raw audio data (slot), 32-Bit Ch/1/32-bit Frame pulse
For AUDEN = 1: & AUDFMT= 3’b010
COMMUNICATION
11I2S -16-bit x2 audio packed left down, 32-Bit Ch/Ch/1/32-bit Frame pulse
10I2S -16-bit x2 audio packed left up, 32-Bit Ch/Ch/1/32-bit Frame pulse
01Reserved
00I2S -24-bit audio packed, 32-Bit Ch/Ch/1/32-bit Frame pulse
For AUDEN = 1: & AUDFMT= 3’b101
COMMUNICATION
11Reserved
10I8S -24-bit raw audio data, 32-Bit Ch, 1/32/128-bit Frame pulse
01I8S -20-bit raw audio data, 32-Bit Ch, 1/32/128-bit Frame pulse
00I8S -16-bit raw audio data, 32-Bit Ch, 1/32/128-bit Frame pulse
For AUDEN = 1: & AUDFMT= 3’b110
COMMUNICATION
11I8S -16-bit x2 audio packed left down, 32-Bit Ch, 1/32/128-bit Frame pulse
10I8S -16-bit x2 audio packed left up, 32-Bit Ch, 1/32/128-bit Frame pulse
01I8S -32-bit data, 32-Bit Ch/128-bit Frame pulse
00I8S -24-bit audio packed, 32-Bit Ch, 1/32/128-bit Frame pulse
For AUDEN = 1: & AUDFMT= 3’b100
COMMUNICATION
11Reserved
10I8S -24-bit MSB al, mute lower bits, 32-Bit Ch, 1/32/128-bit Frame pulse
01I8S -20-bit MSB al, mute lower bits, 32-Bit Ch, 1/32/128-bit Frame pulse
00I8S -16-bit MSB al, mute lower bits, 32-Bit Ch,1/32/128-bit Frame pulse
Note:
  • Channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW
  • Can only be written when ON bit =’0’, and is only valid for AUDEN = 1

Bits 6:4 – AUDFMT[2:0] Audio Protocol Format

Note:
  1. Generate a frame sync pulse on every 8 Serial Words.(Value used by Audio I8S Protocols.)
  2. Generate a frame sync pulse on every 2 Serial Words. (Value used by Audio I2S Protocols.)
  3. Can only be written when ON bit =’0’, and is only valid for AUDEN = 1.
ValueDescription
111Reserved
110I8S Other AM824 formats Mode see note 2
101I8S AM824 Raw audio format Mode see note 2
100I8S Other formats see note 2
011Reserved
010I2S Other AM824 formats Mode see note 1
001I2S AM824 Raw audio format Mode see note 1
000Legacy I2S modes see note 1

Bit 3 – AUDMONO Transmit audio data format

Note: Can only be written when ON bit =’0’, and is only valid for AUDEN = 1.
ValueDescription
0Audio Data is Stereo
1Audio Data is Mono (Each data word is transmitted on both left and right channels)

Bits 1:0 – AUDMOD[1:0] Audio Protocol Mode

Note:
  1. Can only be written when ON bit =’0’, and is only valid for AUDEN = 1.
  2. In I2S Mode, this peripheral functions as if FRMCOINC=0, regardless of its actual value.
  3. In Right or Left Justified Mode (DATFMT_LR), this peripheral functions as if FRMCOINC=1, regardless of its actual value.
  4. When not in PCM/DSP Mode, this peripheral functions as if FRMSYPW=0001, regardless of it actual value.
  5. AUDFMT is used to select between I2S, I8S, PCM audio modes.
ValueDescription
11PCM/DSP Mode
10Reserved
01I2S, I8S right/left Justified Mode -see DATFMT_LR
00I2S, I8S Standard Mode