45.6.7 Data Scramble Control

Note: Access to this register is limited to 32-bit width. Byte level access is not allowed.
Table 45-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: DSCC
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protected, Enable-Protected

Bit 3130292827262524 
 DSCEN DSCKEY[29:24] 
Access R/WWWWWWW 
Reset 0000000 
Bit 2322212019181716 
 DSCKEY[23:16] 
Access WWWWWWWW 
Reset 00000000 
Bit 15141312111098 
 DSCKEY[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 DSCKEY[7:0] 
Access WWWWWWWW 
Reset 00000000 

Bit 31 – DSCEN Data Scramble Enable

Writing '1' to this bit enables the TRAM scrambling function. Reading this bit provides the following information:

ValueDescription
0TRAM scrambling function is disabled
1TRAM scrambling function is enabled

Bits 29:0 – DSCKEY[29:0] Data Scramble Key

The key value used for address and data scrambling and descrambling. Any value written to this field is XOR’ed with the previous data. Writing ‘1’ to CTRLA.SWRST bit (CTRLA <0>) will reset this field to 0. These bits will always return ‘0’ when read.