10.3.2 Bus Matrix Connectivity

The following figure shows the connectivity between Initiators and Targets.

There are six APB shared buses (APB A-F) which provide access to all peripheral SFR registers. This is a shared connection as opposed to a dedicated connection provided by crossbars. Therefore, only one Host may communicate to one particular APB shared bus at a time. During this time, no other Host may communicate to an APB target on that particular APB shared bus. However, there are no restrictions for two initiators to communicate to two different APB shared buses at the same time.

The Flash Control, Read (FCR) part of the NVM Controller provides four AMBA High-Performance Bus (AHB) target ports, numbered 0-3. The number shown for each FCR Initiator shows which of the four ports is used.
Note: Only Port 0 has access to the configuration region of Flash memory (CFM).

Access to Data RAM Memory (DRM) is supported by four AHB target read/write ports (numbered 0-3) on the Multi-Channel RAM Controller (MCRAMC). The number shown for each MCRAMC initiator indicates which port is used.

Figure 10-1. Bus Matrix Connectivity
Note:
  1. The FCR Controller supports four AHB target ports numbered 0-3. The number shown indicates which port is used. Port 0 has access to the CFM region of Flash. Ports 1-3 do not have access.
  2. Data RAM (DRM) access occurs through the Multi-Channel RAM Controller (MCRAMC), which provides four AHB target ports numbered 0-3. The number shown indicates which port is used.
  3. Cortex M7 AHBP connects directly to the PORT module which provides high-speed, low-latency access to the PORT I/O registers only. The CPU uses the PORT APB interface on APB B to access the PORT Control SFR. The DMA can only access the PORT SFR registers through the APB interface on APB B.
  4. Although it is possible to initiate a write transaction with the FCR without generating an exception, this is not a valid transaction and should not be implemented.