45.5.1 Principle of Operation

System bus transactions from the CPU to the security RAM undergo a scrambling routine. The TRAM module modifies both address and data bus information through an algorithm determined by a scrambling key (DSCC.DSCKEY (DSCC<29:0>)). This is performed on both write and read transactions. When the TRAM module receives a Tamper Event (RTC_TAMPER) from the RTC module, it erases the full security RAM and the scrambling key. When it receives a RTC Interval Periodic Event (RTC_PERD) from the RTC module, the TRAM module runs a data remanence routine on the security RAM. The TRAM module can be configured to generate interrupts. The following sections describe each operation in detail.