47.2 Features

The I2S has the following features:

  • Host and client mode support
  • Full-duplex operation with 8/16/20/24/32-bit communication.
  • Status bit to indicate the activity of the SPI
  • Four different clock formats
  • Interrupt event on every byte/half-word/word received
  • Separate transmit and receive buffer events
  • DMA support
  • SDO pin disable option
  • Two 64byte FIFO data buffers are provided, one for transmit and one for receive.
  • Enhanced FSYNC operation
  • Clock TAP in delay
  • Audio CODEC Serial Support
    • I2S protocol
    • I2S left justified
    • I2S right justified
    • I2S 32bit fp audio
    • TDM standard protocol
    • TDM left or right justified
    • TDM,(I2S) AM824 24, 20,16-bit raw audio data
    • TDM 32-bit data
    • TDM 24, 20,16-bit MSB aligned with mute of lower bits.
    • TDM, (I2S) Packed 4x24 bit raw
    • TDM, (I2S) Packed 2x16 bit raw packed upper or lower
  • PCM
  • I2S Transmit Packed data (I2STPD) Host with multiple client transmit operation
  • TDM - Additional features for DSP and Framed SPI host/client protocol support up to 32 slots per frame sync pulse

Codec Feature Set

  • Codecs have complex clock divider modes to support their desired relationships between MCLK, SCLK, and LRCK
    • Most codecs support using a xtal osc so they can generate their own host clock
    • Some CODEC only support receiving MCLK (ala Cirrus LogicCS42*)
    • Codecs contain complex clocking schemes to generate their SCLK and LRCLK from MCLK.
    • Clocks are free running
    • Some codecs support using non-audio MCLK frequency such as USB 12/24/48MHz. these codecs have special divider ratios to achieve accurate PC Audio frequencies and near accurate (1.25%) CD Audio frequencies. (ala wolfson, national, adi, ti)
    • LRCK can have non 50:50 duty cycle - to support USB clocks for MCLK
    • Typical SCLK frequency is 64 Fs (LRCK)
    • Typical MCLK frequency is 125, 128,192, 250, 256, 272, 384, 512 x Fs (i.e., also the divider to achieve the sample rate from MCLK)
    • 125, 250, 272 ratios are for USB clocks
  • I2S interface operates in Host or Client
    • Most systems use the CODEC in host mode, in which case the CODEC provides SCLK and LRCK.
    • Systems that use the CODEC in client mode must provide a Host clock (MCLK), Serial clock (SCLK), and Sample clock (LRCK)that all have a CODEC supported relationship.
  • I2S for ADC and I2S DAC
    • Some have two separate ports to support different sample rates for ADC and DAC
    • Some have 1 SDI and 1 SDO sharing a single LRCK and SCLK forcing the sample rate to be the same for ADC and DAC
  • 16, 20, 24, 32 bit audio data sample sizes
    • Pad LSBs of smaller words to native size
    • Strips LSBs of larger words to native size
  • Data direction is always MSB first
  • Rx/Tx data is sample or transmitted on the rising edge, however timing diagrams show Rx data(to the DAC) driven on the falling edge
  • SCLK= 25Mhz -- 4KHz to 192KHz Sample Rate
  • SCLK= 50Mhz -- 4KHz to 384Khz Sample Rate
  • Audio CODEC Support
    • I2S protocol
    • Left Justified
    • Right Justified (DAC only)
  • PCM (SPI like w/ 1-bit FSync and two data words sent - FSync occurs at Sampling Rate)