22.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock module (MCLK).
A 1024 Hz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter.
The CLK_WDT_OSC clock is sourced from the clock of the internal Ultra Low-Power Oscillator (OSCULP32K).
CAUTION: Watchdog time-out period
variations must be considered when implementing software that uses the WDT to ensure
that the time-out periods used are valid for all devices. Refer to the OSCULP32K
Electrical Specifications section of the Electrical Characteristics
chapter.
The counter clock CLK_WDT_OSC is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.
Note: The FREQM module can be used to calibrate the output of the OSCULP32K clock against a
refererence clock, thereby reducing the uncertainty in setting WDT windows.