1 Silicon Issue Summary

Legend
-
Erratum is not applicable.
X
Erratum is applicable.
PeripheralShort DescriptionValid for Silicon Revision
Rev. B(1)Rev. C
DeviceWriting the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic Loading of Calibration ValuesXX
Write Operation Lost if Consecutive Writes to Specific Address SpacesXX
ADCOne Extra Measurement Performed After Disabling ADC Free-Running ModeXX
ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty CycleXX
Pending Event Stuck When Disabling the ADCXX
CCLConnecting LUTs in Linked Mode Requires OUTEN Set to ‘1’XX
D-latch is Not FunctionalXX
The CCL Must be Disabled to Change the Configuration of a Single LUTXX
NVMCTRLWrong Reset Value of NVMCTRL.CTRLA RegisterXX
PORTMUXSelecting Alternative Output Pin for TCA0 Waveform Output 0-2 also Changes Waveform Output 3-5XX
RTCAny Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler CounterXX
Disabling the RTC Stops the PITXX
TCARestart Will Reset Counter Direction in NORMAL and FRQ ModeXX
TCBMinimum Event Duration Must Exceed the Selected Clock PeriodXX
The TCA Restart Command Does Not Force a Restart of TCBXX
CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM ModeXX
TCDAsynchronous Input Events Not Working When TCD Counter Prescaler is UsedXX
Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is ‘0’ or Dual Slope Mode is UsedXX
USARTTXD Pin Override Not Released When Disabling the TransmitterXX
Full Range Duty Cycle Not Supported When Validating LIN Sync FieldXX
Frame Error on a Previous Message May Cause False Start Bit DetectionXX
Open-Drain Mode Does Not Work When TXD is Configured as OutputXX
Note:
  1. This revision is the initial release of the silicon.