3.5.4 Programming Time
A clarification of the Programming Time section has been made. Table 36-34 has been upgraded from Programming Times to Memory Programming Specifications in the Electrical Characteristics. Functional change is shown in bold.
Table 36-34. Memory Programming Specifications
| Symbol | Description | Min. | Typ.✝ | Max. | Unit | Conditions |
|---|---|---|---|---|---|---|
| Data EEPROM Memory Specifications | ||||||
| EEE* | Data EEPROM byte endurance | 100k | — | — | Erase/Write cycles | -40°C ≤ TA ≤ +105°C |
| tEE_RET | Characteristic retention | — | 40 | — | Year | TA = 55°C |
| tEE_PBC | Page Buffer Clear (PBC) | — | 7 | — | CLKCPU cycles | |
| tEE_EEER | Full EEPROM Erase (EEER) | — | 4 | — | ms | |
| tEE_WP | Page Write (WP) | — | 2 | — | ms | |
| tEE_ER | Page Erase (ER) | — | 2 | — | ms | |
| tEE_ERWP | Page Erase-Write (ERWP) | — | 4 | — | ms | |
| Program Flash Memory Specifications | ||||||
| EFL* | Flash memory cell endurance | 10k | — | — | Erase/Write cycles | -40°C ≤ TA ≤ +105°C |
| tFL_RET | Characteristic retention | — | 40 | — | Year | TA = 55°C |
| VFL_UPDI | VDD for Chip Erase operation | VBODLEVEL0(1) | — | VDDMAX | V | |
| tFL_PBC | Page Buffer Clear (PBC) | — | 7 | — | CLKCPU cycles | |
| tFL_CHER | Chip Erase (CHER) | — | 4 | — | ms | |
| tFL_WP | Page Write (WP) | — | 2 | — | ms | |
| tFL_ER | Page Erase (ER) | — | 2 | — | ms | |
| tFL_ERWP | Page Erase/Write (ERWP) | — | 4 | — | ms | |
| tFL_UPDI | Chip Erase with UPDI | — | 50 | — | ms | 4 KB Flash |
| — | 30 | — | ms | 2 KB Flash | ||
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✝ Data found in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. * These parameters are characterized but not tested in production. Note:
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